PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS

• US 20170278850A1
• Filed: 06/12/2017
• Published: 09/28/2017
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 9,978,773 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Claims

1. A plurality of semiconductor devices, comprising:

a programmable device including a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer including a plurality of input/output characteristics and a plurality of pads in an arrangement; and

a hard-wired device including a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer.

2. The plurality of semiconductor devices of claim 1, wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.

3. The plurality of semiconductor devices of claim 1, wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement.

4. The plurality of semiconductor devices of claim 1, wherein the first pad layer is identical to the second pad layer.

5. The plurality of semiconductor devices of claim 1, wherein the first programmable layer is identical to the second programmable layer.

6. The plurality of semiconductor devices of claim 1, wherein the hard-wire layer comprises a pattern of metal layers.

7. The plurality of semiconductor devices of claim 1, wherein the input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.

8. An apparatus, comprising:

a pad interface circuit operable with a programmable device and further operable with a hard-wired device, wherein the programmable device and the hard-wired device are interchangeable, and wherein;

the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the pad interface circuit; and

the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the pad interface circuit.

9. The apparatus of claim 8, wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.

10. The apparatus of claim 8, wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement.

11. The apparatus of claim 8, wherein the first pad layer is identical to the second pad layer.

12. The apparatus of claim 8, wherein the first programmable layer is identical to the second programmable layer.

13. The apparatus of claim 8, wherein the hard-wire layer comprises a pattern of metal layers.

14. The apparatus of claim 8, wherein input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.

15. An apparatus, comprising:

a peripheral device operable with a programmable device, further operable with a hard-wired device, and including an interface configuration, wherein the programmable device and the hard-wired device are interchangeable, and wherein;

the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the interface configuration; and

the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the interface configuration.

16. The apparatus of claim 15, wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.

17. The apparatus of claim 15, wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement, and wherein the hard-wire layer comprises a pattern of metal layers.

18. The apparatus of claim 15, wherein the first pad layer is identical to the second pad layer.

19. The apparatus of claim 15, wherein the first programmable layer is identical to the second programmable layer.

20. The apparatus of claim 15, wherein input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.