INTEGRATED VOLTAGE REGULATOR WITH IN-BUILT PROCESS, TEMPERATURE AND AGING COMPENSATION

• US 20170279440A1
• Filed: 06/12/2017
• Published: 09/28/2017
• Est. Priority Date: 07/22/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: PANT, Sanjay, RAJA, Tezaswi, CHARNAS, Andy
• Granted Patent: US 10,200,022 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Claims

1. A method for regulating voltage for a processor, said method comprising:

requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor;

comparing the target clock frequency to a first signal to generate an error signal;

using the error signal, generating a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform;

generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor; and

providing the output regulator voltage as an input to a critical path monitoring circuit, wherein further the first signal is a delay value from the critical path monitoring circuit.

6. The method of claim 1, wherein said critical path monitoring circuit comprises a canary circuit.

7. The method of claim 1, wherein said critical path monitoring circuit comprises an in-situ critical path delay monitor.

2. The method of claim 2, wherein the comparing is performed by a phase detector.

3. The method of claim 2, further comprising:

adjusting the output regulator voltage wherein the critical path monitoring circuit maintains the target clock frequency across all temperature and aging variations.

4. The method of claim 3, wherein said adjusting comprises reducing the output regulator voltage until right before the critical path monitoring circuit signals a fail signal.

5. The method of claim 4, wherein said adjusting is performed continuously in order to operate said processor at a lowest possible voltage.

8. A method for regulating voltage for a processor, said method comprising:

requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor;

comparing the target clock frequency to a plurality of first signals to generate an error signal;

using the error signal, generating a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform;

generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor; and

providing the output regulator voltage as an input to a plurality of critical path monitoring circuits, wherein further the plurality of first signals comprise delay values from the plurality of critical path monitoring circuits.

9. The method of claim 8, wherein the comparing is performed by an array of phase detectors.

10. The method of claim 9, further comprising:

adjusting the output regulator voltage wherein the plurality of critical path monitoring circuits maintain the target clock frequency across all temperature and aging variations.

11. The method of claim 10, wherein said adjusting comprises reducing the output regulator voltage until right before at least one of the critical path monitoring circuits signals a fail signal.

12. The method of claim 11, wherein said adjusting is performed continuously in order to operate said processor at a lowest possible voltage.

13. The method of claim 8, wherein said plurality of critical path monitoring circuits comprise replica canary circuits.

14. The method of claim 8, wherein said plurality of critical path monitoring circuits comprise in-situ critical path delay monitors.

15. An apparatus for regulating a processor voltage, said apparatus comprising:

a plurality of critical path monitoring circuits operating at an output regulator voltage;

a plurality of phase detectors operable to compare a plurality of delay values corresponding to the plurality of critical path monitoring circuits to a target clock frequency in order to generate an error signal, wherein each of the plurality of delay values represents a critical path delay for a respective critical path of a processor; and

a circuit operable to generate the output regulator voltage using the error signal, wherein the output regulator voltage is operable to provide power to the processor.

16. The apparatus of claim 15, wherein the circuit comprises:

a proportional-integral-derivative (PID) controller operable to compensate the error signal to generate a duty cycle control signal;

a digital pulse-width modulation block and a pair of power FETs operable to convert the duty cycle control signal into a periodic waveform; and

a discrete inductor, wherein the periodic waveform is operable to periodically switch the discrete inductor in order to generate the output regulator voltage.

17. The apparatus of claim 15, further comprising:

a PLL module operable to convert a target frequency value inputted into the PLL module into the target clock frequency.

18. The apparatus of claim 15, wherein the output regulator voltage is operable to be adjusted wherein the plurality of critical path monitoring circuits meet the target clock frequency across all temperature and aging variations.

19. The apparatus of claim 15, wherein the target clock frequency is a fixed frequency.

20. The apparatus of claim 15, wherein the plurality of critical path monitoring circuits, the plurality of phase detectors, the circuit and the processor are integrated onto a same die.