DECREASING THE DATA HANDOFF INTERVAL FOR A RESERVED CACHE LINE BASED ON AN EARLY INDICATION OF A SYSTEMWIDE COHERENCE RESPONSE

• US 20170293558A1
• Filed: 04/11/2016
• Published: 10/12/2017
• Est. Priority Date: 04/11/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: GUTHRIE, GUY L., JACKSON, JONATHAN R., STARKE, WILLIAM J., STUECHELI, JEFFREY A., WILLIAMS, DEREK E.
• Granted Patent: US 10,157,134 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request. In response to the early indication and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

Claims

1. A method of data processing in a multiprocessor data processing system including multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies, the method comprising:

in response to receipt of a load-and-reserve request from a first processor core, a first cache memory in a first vertical cache hierarchy supporting the first processor core issuing on the system interconnect a memory access request for a target cache line of the load-and-reserve request;

responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receiving from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request; and

in response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

2. The method of claim 1, and further comprising:

the first cache memory sourcing the target cache line to a third cache in a third vertical cache hierarchy prior to receipt of the systemwide combined response.

3. The method of claim 1, and further comprising:

in response to receipt of the early indication of the systemwide coherence response, the first cache memory commencing a protection window in which the first cache memory protects its acquisition of coherence ownership of the target cache line; and

continuing the protection window for at least a wait interval following processing of the load-and-reserve request during which the first cache memory awaits receipt of a store-conditional request from the first processor core.

4. The method of claim 3, and further comprising ending the protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to completion of processing of the store-conditional request.

5. The method of claim 3, wherein:

the protection window is a first protection window; and

the method further comprises ending the first protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to initiation of a second protection window by the first cache memory in response to receipt of the store-conditional request.

6. The method of claim 3, and further comprising:

the first cache memory allocating a read-claim state machine to manage the request in response to receipt of the load-and reserve request from the first processor core; and

the first cache memory deallocating the read-claim state machine in response to a later to occur of receipt of the systemwide coherence response and ending of the protection window.

7. The method of claim 1, wherein the first cache memory initiating processing to update the target cache line in the first cache memory comprises the first cache memory initiating processing to update the target cache line in the first cache memory in response to receipt of a store-conditional request of the first processor core.

8. A processing unit for a multiprocessor data processing system, the processing unit comprising:

a processor core;

interconnect logic configured to couple the processing unit to a system interconnect of the multiprocessor data processing system;

a first vertical cache hierarchy supporting the processor core, the first vertical cache hierarchy including a first cache memory that is configured to;

in response to receipt of a load-and-reserve request from the processor core, issue on the system interconnect a memory access request for a target cache line of the load-and-reserve request;

responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, receive from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request; and

in response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, initiate processing to update the target cache line in the first cache memory.

9. The processing unit of claim 8, wherein the first cache memory is further configured to source the target cache line to a third cache in a third vertical cache hierarchy prior to receipt of the systemwide combined response.

10. The processing unit of claim 8, wherein the first cache memory is further configured to:

in response to receipt of the early indication of the systemwide coherence response, commence a protection window in which the first cache memory protects its acquisition of coherence ownership of the target cache line; and

continue the protection window for at least a wait interval following processing of the load-and-reserve request during which the first cache memory awaits receipt of a store-conditional request from the first processor core.

11. The processing unit of claim 10, wherein the first cache memory is further configured to end the protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to completion of processing of the store-conditional request.

12. The processing unit of claim 10, wherein:

the protection window is a first protection window; and

the first cache memory is further configured to end the first protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to initiation of a second protection window by the first cache memory in response to receipt of the store-conditional request.

13. The processing unit of claim 10, wherein the first cache memory is further configured to:

allocate a read-claim state machine to manage the request in response to receipt of the load-and reserve request from the first processor core; and

deallocate the read-claim state machine in response to a later to occur of receipt of the systemwide coherence response and ending of the protection window.

14. The processing unit of claim 8, wherein the first cache memory is further configured to initiate processing to update the target cache line in the first cache memory in response to receipt of a store-conditional request of the first processor core.

15. A multiprocessing data processing system, comprising:

first, second and third processing units in accordance with claim 8; and

the system interconnect coupling the first, second and third processing units.

16. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a multiprocessor data processing system, the processing unit comprising;

a processor core;

interconnect logic configured to couple the processing unit to a system interconnect of the multiprocessor data processing system;

a first vertical cache hierarchy supporting the processor core, the first vertical cache hierarchy including a first cache memory that is configured to;

in response to receipt of a load-and-reserve request from the processor core, issue on the system interconnect a memory access request for a target cache line of the load-and-reserve request;

responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, receive from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request; and

in response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, initiate processing to update the target cache line in the first cache memory.

17. The design structure of claim 16, wherein the first cache memory is further configured to source the target cache line to a third cache in a third vertical cache hierarchy prior to receipt of the systemwide combined response.

18. The design structure of claim 16, wherein the first cache memory is further configured to:

in response to receipt of the early indication of the systemwide coherence response, commence a protection window in which the first cache memory protects its acquisition of coherence ownership of the target cache line; and

continue the protection window for at least a wait interval following processing of the load-and-reserve request during which the first cache memory awaits receipt of a store-conditional request from the first processor core.

19. The design structure of claim 18, wherein the first cache memory is further configured to end the protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to completion of processing of the store-conditional request.

20. The design structure of claim 18, wherein:

the protection window is a first protection window; and

the first cache memory is further configured to end the first protection window asynchronously to receipt by the first cache memory of the systemwide coherence response in response to initiation of a second protection window by the first cache memory in response to receipt of the store-conditional request.