METHOD AND SYSTEM FOR A SEMICONDUCTOR DEVICE WITH INTEGRATED TRANSIENT VOLTAGE SUPPRESSION
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Abstract
A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.
9 Citations
32 Claims
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1-22. -22. (canceled)
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23. A thyristor assembly with integrated transient voltage suppression on a single semiconductor substrate comprising:
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a thyristor formed of a wide band gap material, said thyristor comprising a gate terminal, a cathode terminal, an anode terminal and a lower base contact terminal, said thyristor further comprising a predetermined maximum allowable gate voltage value; and a transient voltage suppression (TVS) device formed of a wide band gap material, said TVS device formed with the thyristor as a single semiconductor device, said TVS device electrically coupled to said thyristor between at least one of said electrodes and a ground connected electrode, said TVS device including a turn-on voltage selected to be less than the predetermined maximum electrical terminal voltage value. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification