GATE DRIVER AND CONFIGURATION SYSTEM AND CONFIGURATION METHOD THEREOF

• US 20170301305A1
• Filed: 09/27/2016
• Published: 10/19/2017
• Est. Priority Date: 10/16/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Gao, Xianyong, Hsu, Yihjen, Xiao, Lijun, Hou, Shuai, Xu, Bo, Liang, Lisheng, Fu, Siqing, Shang, Fei, Qiu, Haijun
• Granted Patent: US 10,482,836 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A gate driver, a configuration system, and configuration method thereof, is provided. The gate driver is used for providing a gate drive signal for a TFT array substrate, and comprises at least a drive capability detection module and a drive capability adjustment module. The configuration system is configured to configure the driving capabilities of a plurality of gate drivers, and comprises a controller provided outside the plurality of gate drivers. The driving capability of the gate driver becomes adjustable and configurable. The well balance of the drive capabilities of the drive control signals received by the different TFT array regions driven by the plurality of gate drivers configured by the configuration system can avoid the occurrence of a splitting-screen phenomenon.

Claims

1. A gate driver for providing a gate drive signal for a thin film transistor array substrate, the gate driver comprising:

a driving capability detection module configured to detect a driving capability of the gate drive signal and output a detection signal of the driving capability; and

a driving capability adjustment module configured to adjust the driving capability of the gate drive signal based on the detection signal of the driving capability.

2. The gate driver according to claim 1, wherein the driving capability detection module is configured to receive at least a feedback signal collected from the gate drive signal and to detect the driving capability of the gate drive signal based at least on the feedback signal, the driving capability being represented by a rising time taken by the gate drive signal in the form of voltage pulse signal to rise from a low level to a high level.

3. The gate driver according to claim 1, wherein the driving capability adjustment module is configured to adjust the driving capability of the gate drive signal based on an adjustment instruction generated based on the detection signal and configured and input from outside.

4. The gate driver according to claim 1, wherein the driving capability detection module comprises:

a comparator configured to have a first input end input with a reference voltage signal and a second input end input with the feedback signal collected from the gate drive signal, wherein the comparator compares the feedback signal with the reference voltage signal to determine whether the gate drive signal has risen from a low level to the reference voltage; and

a timing sub-module for determining the time period taken by the gate drive signal to rise from the low level to the reference voltage and outputting the detection signal based on the time period.

5. The gate driver according to claim 4, wherein the timing sub-module comprises a counter which counts the time period taken by the gate drive signal to rise from the low level to the reference voltage using a standard clock signal and outputs a count value.

6. The gate driver according to claim 4, wherein the driving capability detection module comprises a reference voltage signal providing sub-module comprising a first resistor and a second resistor arranged in series, the first input end of the comparison sub-module being electrically connected to a node between the first resistor and the second resistor.

7. The gate driver according to claim 5, wherein the reference voltage signal providing sub-module is configured as a signal source generating the gate drive signal.

8. The gate driver according to claim 1, wherein the driving capability adjustment module comprises:

a driving capability adjustment component provided in a push-pull output circuit of the gate driver, and

a register for configurably storage of the adjustment instruction which is a digital signal;

wherein the driving capability adjustment component is adjusted and controlled by the adjustment instruction in the register.

9. The gate driver according to claim 8, wherein the driving capability adjustment component is a digital potentiometer, a digital capacitor, or a circuit formed by a digital potentiometer or a digital capacitor.

10. The gate driver according to claim 8, wherein the push-pull output circuit comprises a first MOS transistor and a second MOS transistor arranged in series;

wherein the first MOS transistor is connected to a signal source having a high level, and the second MOS transistor is connected to a signal source having a low level, and the driving capability adjusting component is provided in series between the first MOS transistor and the second MOS transistor;

wherein the feedback signal is collected at a node between the second MOS transistor in the push-pull output circuit and the driving capability adjusting component.

11. The gate driver according to claim 1, wherein the detection signal is a digital signal.

12. A configuration system for configuring driving capabilities of a plurality of gate drivers, the plurality gate drivers being used for driving different thin film transistor array regions of a thin film transistor array substrate, the configuration system comprising:

the plurality of gate drivers wherein each gate driver comprises a driving capability detection module configured to detect a driving capability of the gate drive signal and output a detection signal of the driving capability; and

a driving capability adjustment module configured to adjust the driving capability of the gate drive signal based on the detection signal of the driving capability;

a controller for storing said detection signals output from the plurality of gate drivers and comparing the respective detection signals corresponding to the plurality of gate drivers to output different adjustment instructions corresponding to each of the plurality of gate drivers, such that the driving capabilities of the various drive control signals obtained after the gate drive signals are output from each of the plurality gate drivers to the respective thin film transistor array regions are relatively consistent.

13. The configuration system according to claim 12, wherein the plurality of gate drivers are provided on a same thin film transistor array substrate.

14. The configuration system according to claim 12, wherein the controller is configured with a driving capability configuration rule and outputs the adjustment instructions based on a comparison result between the configuration rule and the detection signals.

15. The configuration system according to claim 14, wherein the driving capability configuration rule is set according to the driving capability differences between the gate drive signals output by the plurality of gate drivers and the external wiring conditions corresponding to the plurality of gate drivers.

16. The configuration system according to claim 12, wherein the detection signal is output through an external pin of the gate driver and is transmitted to the controller via an I2C communication line external to the gate driver.

17. A method of configuring driving capabilities of a plurality of gate drivers, comprising the steps of:

receiving feedback signals collected from the gate drive signals output from the plurality of gate drivers;

detecting driving capabilities of the gate driving signals based on the feedback signals, and outputting detection signals that reflect the driving capabilities of the gate driving signals;

comparing the respective detection signals corresponding to the plurality of gate drivers to output different adjustment instructions corresponding to the different gate drivers,

adjusting the driving capabilities of the gate drive signals in accordance with the adjustment instructions such that the driving capabilities of the various drive control signals obtained after the gate drive signals are output from the various gate drivers to the respective thin film transistor array regions are relatively consistent.

18. The method according to claim 17, further comprises driving the same thin film array substrate with the output signals of the plurality of gate drivers after adjusted and configured.

19. The method according to claim 17, wherein the adjustment instruction is generated based on a comparison result between a pre-set driving capability configuration rule and the detection signal.

20. The method according to claim 19, wherein the driving capability configuration rule is set according to the driving capability difference between the gate drive signals output by the plurality of gate drivers and/or the external wiring conditions corresponding to the plurality of gate drivers.