IEEE 1149.1 INTERPOSER METHOD AND APPARATUS

• US 20170315172A1
• Filed: 07/20/2017
• Published: 11/02/2017
• Est. Priority Date: 02/07/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Granted Patent: US 10,267,854 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Claims

1. An analog input boundary scan cell comprising:

(a) a digital scan cell having a test data input (TDI), a test data output (TDO), a compare input, a first switch output, and a control input;

(b) a comparator having a voltage reference input, a functional input and a compare output coupled to the compare input;

(c) a first analog switch having a control input coupled to the first switch output, a first voltage input at a first voltage, a second voltage input at a second voltage different than the first voltage, and a first switch output; and

(d) a second analog switch having a functional input coupled to the functional input of the comparator, a first switch input coupled to the first switch output, a mode input, and a second switch output.

2. The analog input boundary scan cell of claim 1 in which the digital scan cell includes a capture, shift update (CSU) scan cell.

3. The analog input boundary scan cell of claim 1 including a unity gain voltage follower amplifier having an input coupled to the second switch output.

4. The analog input boundary scan cell of claim 1 in which the comparator functional input receives a time varying analog signal.

5. The analog input boundary scan cell of claim 1 in which the first voltage is voltage level high and the second voltage is voltage level low.

6. The analog input boundary scan cell of claim 1 in which the first switch output controls switching the first switch output between the first voltage and the second voltage.

7. The analog input boundary scan cell of claim 1 in which the mode input controls switching the second switch output between the first switch output and the functional input.

8. An analog input boundary scan cell comprising:

(a) a functional input;

(b) a functional output;

(c) a voltage reference input;

(d) a test data input;

(e) a test data output;

(f) a control input;

(g) a mode input;

(h) a first voltage input at a first voltage; and

(i) a second voltage input at a second voltage different than the first voltage.

9. The analog input boundary scan cell of claim 8 including a digital scan cell having an input coupled to the functional input.

10. The analog input boundary scan cell of claim 8 including a digital scan cell having an output coupled to the functional output.

11. The analog input boundary scan cell of claim 8 including a digital scan cell and a switch coupling the first and second voltage inputs to the functional output.

12. The analog input boundary scan cell of claim 8 in which the digital scan cell is coupled to the test data input, the test data input, and the control input.