VECTOR SIGNALING CODES FOR DENSELY-ROUTED WIRE GROUPS

• US 20170317855A1
• Filed: 04/27/2017
• Published: 11/02/2017
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Hormati, Ali, Tajalli, Armin
• Granted Patent: US 10,333,741 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/4919 using balanced multilevel codes H04L25/4927 takes precedence

Abstract

Methods and systems are described for receiving signal elements corresponding to a first group of symbols of a vector signaling codeword over a first densely-routed wire group of a multi-wire bus at a first set of multi-input comparators (MICs), receiving signal elements corresponding to a second group of symbols of the vector signaling codeword over a second densely-routed wire group of the multi-wire bus at a second set of MICs, and receiving signal elements corresponding to the first and the second groups of symbols of the vector signaling codeword at a global MIC.

Claims

1. A method comprising:

receiving signal elements corresponding to a first group of symbols of a vector signaling codeword over a first densely-routed wire group of a multi-wire bus at a first set of multi-input comparators (MICs);

receiving signal elements corresponding to a second group of symbols of the vector signaling codeword over a second densely-routed wire group of the multi-wire bus at a second set of MICs; and

receiving signal elements corresponding to the first and the second groups of symbols of the vector signaling codeword at a global MIC.

2. The method of claim 1, wherein the symbols of the vector signaling code represent a superposition of a plurality of subchannel vectors, each sub-channel vector weighted by a corresponding antipodal weight.

3. The method of claim 2, wherein the first group of symbols of the vector signaling codeword correspond to a superposition of a first subset of the plurality of subchannel vectors and wherein the second group of symbols of the vector signaling codeword correspond to a superposition of a second subset of the plurality of subchannel vectors.

4. The method of claim 3, wherein the first and second subsets of the plurality of subchannel vectors share a single subchannel vector.

5. The method of claim 1 wherein the signal elements of the first group of subchannel vectors are locally symmetric over the first densely-routed wire group and the signal elements of the second group of subchannel vectors are locally symmetric over the second densely-routed wire group.

6. The method of claim 1, further comprising generating a first set of sampled outputs of the first set of MICs using a first sampling clock and generating a second set of sampled outputs of the second set of MICs using a second sampling clock;

forming a comparison of (i) a sum of the first set of sampled outputs and (ii) the second set of sampled outputs; and

sampling the comparison using a third sampling clock.

7. The method of claim 1 wherein the first and second densely-routed wire group comprises three conductors.

8. The method of claim 1 wherein the first densely-routed wire group comprises three conductors and the second densely-routed wire group comprises two conductors.

9. The method of claim 1, further comprising receiving signal elements corresponding to a third group of symbols of the vector signaling codeword over a third densely-routed wire group of the multi-wire bus at a third set of MICs, and wherein the global MIC is further configured to receive the signal elements corresponding to the third group of symbols of the vector signaling codeword.

10. The method of claim 9, wherein the first, second, and third densely-routed wire groups each comprise three conductors.

11. An apparatus comprising:

a first set of multi-input comparators (MICs) connected to a first densely-routed wire group of a multi-wire bus, the first set of MICs configured to receive signal elements corresponding to a first group of symbols of a vector signaling codeword;

a second set of MICs connected to a second densely-routed wire group of the multi-wire bus, the second set of MICs configured to receive signal elements corresponding to a second group of symbols of the vector signaling codeword;

a global MIC connected to the first and second densely-routed wire groups configured to receive signal elements corresponding to the first and second groups of symbols of the vector signaling codeword.

12. The apparatus of claim 11, wherein the global MIC has a first input connected to all the wires of the first densely-routed wire group and a second input connected to all the wires of the second densely-routed wire group.

13. The apparatus of claim 11, further comprising a clock recovery circuit configured to generate a first sampling clock for the first set of MICs and a second sampling clock for the second set of MICs, and wherein the global MIC obtains signal samples based on signal elements received from the first densely-routed wire group according to the first sampling clock, and obtains signal samples of signal elements based on signal elements received from the second densely-routed wire group according to the second sampling clock.

14. The apparatus of claim 13, wherein the clock recovery circuit is configured to obtain a symbol clock received on a differential pair of wires.

15. The apparatus of claim 13, wherein the clock recovery circuit is configured to receive a symbol clock from a MIC in the first or second set of MICs or the global MIC.

16. The apparatus of claim 13, wherein the global MIC is configured to generate a comparison of a linear combination of the signal samples obtained from the first densely-routed wire group and the signal samples obtained from the second densely-routed wire group, and wherein the global MIC comprises a sampler configured to receive a third sampling clock, the third sampling clock having a phase delay with respect to the first and second sampling clocks, the sampler configured to sample the comparison of the linear combination.

17. The apparatus of claim 16, wherein the comparison of the linear combination corresponds to a sum of the signal samples received from the first densely-routed wire group compared to a sum of the signal samples received from the second densely-routed wire group.

18. The apparatus of claim 11, wherein the first and second densely-routed wire groups comprise intra-group symmetry with respect to corresponding sub-channel vectors carried by the respective densely-route wire groups.

19. The apparatus of claim 11, further comprising an isolation medium separating the first and second densely-routed wire groups.

20. The apparatus of claim 11, further comprising a third set of MICs connect to a third densely-routed wire group of the multi-wire bus, the third set of MICs configured to receive signal elements corresponding to a third group of symbols of the vector signaling codeword, and wherein the global MIC is further connected to the third densely-routed wire group and configured to receive signal elements corresponding to the third group of symbols of the vector signaling codeword.