PIXEL ARRAY WITH SHARED PIXELS IN A SINGLE COLUMN AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS

• US 20170332030A1
• Filed: 07/29/2017
• Published: 11/16/2017
• Est. Priority Date: 10/01/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yin, Zhiping, Fan, Xiaofeng, Li, Xiangli
• Granted Patent: US 9,979,915 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region.

Claims

1. An imager, comprising:

a pixel array, including—

a floating diffusion region,

a source follower transistor having a gate coupled to the floating diffusion region,

a plurality of pixels associated with a plurality of colors and configured to transfer charge to the floating diffusion region, the plurality of pixels arranged in a first column, the plurality of pixels including at least two pixels associated with a first one of the plurality of colors; and

control circuitry operably coupled to the pixel array, wherein the control circuitry is configured to successively read out onto a column line image signals corresponding to the charge transferred to the floating diffusion region via each of the plurality of pixels.

2. The imager of claim 1 wherein the floating diffusion region is a first floating diffusion region, the source follower transistor is a first source follower transistor, the plurality of pixels is a first plurality of pixels, and the column line is a first column line, and wherein the pixel array further includes:

a second floating diffusion region;

a second source follower transistor having a gate coupled to the second floating diffusion region;

a second plurality of pixels associated with a second plurality of colors including a second color different than the first one of the plurality of colors, the second plurality of pixels configured to transfer charge to the second floating diffusion region and arranged in a second column, the second plurality of pixels including at least two pixels associated with a second one of the second plurality of colors;

wherein the control circuitry is further configured to successively read out onto a second column line image signals corresponding to the charge transferred to the floating diffusion region by each of the second plurality of pixels.

3. The imager of claim 2 further comprising a ground line between the first column and the second column.

4. The imager of claim 2 wherein the imager further comprises:

a first column line transistor coupled to the first column; and

a second column line transistor coupled to the second column.

5. The imager of claim 1, further comprising a ground line extending along the column line.

6. The imager of claim 1 wherein the control circuitry is further configured to read out one of the plurality of pixels at a time that is (1) after readout of one of the at least two pixels and (2) before readout of another one of the at least two pixels.

7. The imager of claim 1, further comprising a reset transistor switchably coupling the floating diffusion region to a reset line, wherein the control circuitry is further configured to reset the floating diffusion region at a time that is (1) after readout of one of the at least two pixels and (2) before readout of one of the plurality of pixels that is not one of the at least two pixels.

8. The imager of claim 1 wherein each of the first plurality of pixels includes a photosensor and a transfer transistor coupled to the photosensor, and wherein the control circuitry is further configured to transfer charge generated by the photosensor to the floating diffusion region.

9. The imager of claim 1 further comprising:

a sample and hold circuit; and

a column line transistor coupling the source follower transistor to the sample and hold circuit.

10. A pixel array comprising:

a floating diffusion region;

a source follower transistor having a gate coupled to the floating diffusion region; and

a plurality of pixels associated with a plurality of colors and configured to transfer charge to the floating diffusion region, the plurality of pixels arranged in a first column, the plurality of pixels including at least two pixels associated with a first one of the plurality of colors.

11. The pixel array of claim 10 further comprising a column line transistor operably coupling the source follower transistor to a sample and hold circuit.

12. The pixel array of claim 10 wherein the floating diffusion region is a first floating diffusion region and the source follower transistor is a second source follower transistor, and wherein the pixel array further comprises:

a second floating diffusion region;

a second follower transistor having a gate coupled to the second floating diffusion region; and

a second plurality of pixels associated with a second plurality of colors including a second color different than the first one of the plurality of colors, the second plurality of pixels configured to transfer charge to the second floating diffusion region and arranged in a second column.

13. The pixel array of claim 12, wherein the second plurality of pixels includes at least two pixels associated with a second one of the second plurality of colors.

14. The pixel array of claim 10, further comprising a reset transistor switchably coupling the floating diffusion region to a reset line over which the floating diffusion region receives a reset signal.

15. The pixel array of claim 10 wherein each of the plurality of pixels includes a photosensor and a transfer transistor configured to transfer photo-generated charge from the photosensor to the floating diffusion region.