Pulse-by-Pulse Compliance Voltage Generation for an Implantable Stimulator

• US 20170333719A1
• Filed: 08/08/2017
• Published: 11/23/2017
• Est. Priority Date: 05/17/2012
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Marnfeldt, Goran N., Shi, Jess
• Granted Patent: US 10,363,423 B2
• Time in Patent Office: Days
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/36146 specified by the stimulation parameters
• CPC Class Codes: A61N 1/36153 Voltage A61N1/3616 takes precedence
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply

Abstract

Circuitry for generating a compliance voltage (V+) for the current sources and/or sinks in an implantable stimulator device in disclosed. The circuitry assesses whether V+ is optimal for a given pulse, and if not, adjusts V+ for the next pulse. The circuitry uses amplifiers to measure the voltage drop across active PDACs (current sources) and NDAC (current sinks) at an appropriate time during the pulse. The measured voltages are assessed to determine whether they are high or low relative to optimal values. If low, a V+ regulator is controlled to increase V+ for the next pulse; if not, the V+ regulator is controlled to decrease V+ for the next pulse. Through this approach, gradual changes that may be occurring in the implant environment can be accounted for, with V+ adjusted on a pulse-by-pulse basis to keep the voltage drops at or near optimal levels for efficient DAC operation.

Claims

1. Circuitry configured to adjust a compliance voltage in an implantable stimulator device, comprising:

a current generator configured to provide a current pulse to at least one electrode;

a minimum determining circuit configured to determine a minimum value of a voltage across the current generator that occurs during a duration of the current pulse; and

regulator circuitry configured to adjust the compliance voltage that powers the current generator, wherein the regulator circuitry is controlled by a control signal derived from the minimum value.

2. The circuitry of claim 1, wherein the minimum determining circuit comprises:

an amplifier configured to receive the voltage at a first input, and the minimum value at a second input;

a diode coupled between an output of the amplifier and the minimum value; and

a storage capacitor coupled between the minimum value and ground.

3. The circuitry of claim 2, wherein the minimum determining circuitry further comprises a pull up transistor configured to pull up the minimum value after the minimum value of the voltage across the current generator has been determined.

4. The circuitry of claim 1, wherein the current generator comprises a current source configured to source the current pulse to the at least one electrode.

5. The circuitry of claim 1, wherein the current generator comprises a current sink configured to sink the current pulse from the at least one electrode.

6. The circuitry of claim 1, wherein the compliance voltage is connected to the current generator.

7. The circuitry of claim 1, wherein the compliance voltage is coupled to the current generator through a patient'"'"'s tissue.

8. Circuitry configured to adjust a compliance voltage in an implantable stimulator device, comprising:

a source circuit coupled to a compliance voltage, wherein the source circuit is configured to provide a first current pulse to at least a first electrode;

a sink circuit coupled to a reference voltage, wherein the sink circuit is configured to sink the first current pulse from at least a second electrode;

first minimum determining circuitry configured determine a minimum first value of a first voltage across the source circuit that occurs during a duration of the first current pulse;

second minimum determining circuitry configured determine a minimum second value of a second voltage across the sink circuit that occurs during the duration of the first current pulse; and

regulator circuitry configured to adjust the compliance voltage, wherein the regulator circuitry is controlled by a control signal derived from the minimum first value and the minimum second value.

9. The circuitry of claim 8, further comprising:

a first comparator configured to compare the minimum first value to an optimal first voltage and to produce a first digital signal indicating whether the minimum first value is high or low relative to the optimal first voltage; and

a second comparator configured to compare the minimum second value to an optimal second voltage and to produce a second digital signal indicating whether the minimum second value is high or low relative to the optimal second voltage,

wherein the control signal is derived from the first and second digital signals.

10. The circuitry of claim 9, wherein the control signal enables the regulator circuitry when either the first or second digital signal indicates that the minimum first or second value is low compared respectively to the first or second optimal voltage.

11. The circuitry of claim 9, wherein the first and second comparators compare the minimum first and second values respectively to the optimal first and second voltages after the first current pulse.

12. The circuitry of claim 8, further comprising a summing circuit to add the first minimum value and the second minimum value to produce a summed signal, wherein the control signal is derived from the summed signal.

13. The circuitry of claim 12, further comprising a comparator configured to compare the summed signal to an optimal summed signal and to produce the control signal indicating whether the summed signal is high or low relative to the optimal summed signal.

14. The circuitry of claim 8, wherein the regulator circuitry comprises a boost converter.

15. The circuitry of claim 8, wherein the control signal is digital.

16. The circuitry of claim 8, wherein the regulator circuitry is configured to adjust the compliance voltage for a next current pulse in accordance with the control signal.

17. The circuitry of claim 8, further comprising a first amplifier configured to determine the first voltage across the source circuit during the duration of the first current pulse, and a second amplifier configured to determine the second voltage across the sink circuit during the duration of the first current pulse.

18. The circuitry of claim 8, wherein the reference voltage comprises ground.