POWER MOSFET

• US 20170338309A1
• Filed: 06/14/2016
• Published: 11/23/2017
• Est. Priority Date: 05/18/2016
• Status: Active Grant

• Current Assignee: Excelliance Mos Corporation
• Original Assignee: Excelliance Mos Corporation
• Inventors: Liu, Chu-Kuang
• Granted Patent: US 9,941,357 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. The semiconductor layer is formed on the substrate and has at least one trench. The first gate is located inside the trench. The second gate is located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is located between the first gate and the semiconductor layer. The first CVD oxide layer is located between the first gate and the second gate. The gate oxide layer is generally located between the second gate and the semiconductor layer.

Claims

1. A power metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:

a substrate;

a semiconductor layer formed on the substrate, and the semiconductor layer has at least one trench;

a first gate located inside the trench;

a second gate located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, the second portion is located between the semiconductor layer and the first portion, and the second portion is located at a sidewall of the first portion and forms the second gate with the first portion;

a thermal oxide layer located between the first gate and the semiconductor layer;

a first chemical vapor deposition (CVD) oxide layer located between the first gate and the second gate, and the first CVD oxide layer is directly in contact with the first portion and the second portion of the second gate; and

a gate oxide layer located between the second gate and the semiconductor layer.

2. The power MOSFET of claim 1, wherein the thermal oxide layer is further located between the first CVD oxide layer and the first gate.

3. The power MOSFET of claim 1, wherein the gate oxide layer is further extended between the first CVD oxide layer and the semiconductor layer.

4. The power MOSFET of claim 1, further comprising:

a second CVD oxide layer located between the first gate and the thermal oxide layer; and

a silicon nitride layer located between the second CVD oxide layer and the thermal oxide layer.

5. The power MOSFET of claim 3, wherein the second portion of the second gate is further extended downward between the first CVD oxide layer and the gate oxide layer.

6. The power MOSFET of claim 1, wherein the second portion in the second gate further covers the first portion.

7. The power MOSFET of claim 1, wherein a material of the first gate comprises metal, polysilicon, amorphous silicon, or a combination thereof.

8. The power MOSFET of claim 1, wherein a material of the second gate comprises metal, polysilicon, amorphous silicon, or a combination thereof.

9. The power MOSFET of claim 1, wherein a material of the first portion is different from a material of the second portion.

10. The power MOSFET of claim 1, wherein the first CVD oxide layer and the second CVD oxide layer each independently comprise a high-temperature CVD oxide (HTO) layer or are formed by using tetraethyl orthosilicate as a raw material.

11. The power MOSFET of claim 1, wherein the first gate has a rounded corner.