ENHANCEMENT MODE FET GATE DRIVER IC

• US 20170346475A1
• Filed: 05/25/2017
• Published: 11/30/2017
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: de Rooij, Michael A., Reusch, David C., Biswas, Suvankar
• Granted Patent: US 10,243,546 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H03K 17/0406 in composite switches
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165

Abstract

A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.

Claims

1. An integrated gate driver circuit for driving an enhancement mode GaN field effect transistor, comprising the following elements fully integrated in a single chip:

a gate driver, comprising;

a logic inverter circuit;

a level shifter circuit having an input and an output, the level shifter circuit converting a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output; and

an output stage for driving an FET; and

an undervoltage lockout circuit connected to the gate driver, comprising;

a voltage reference circuit for generating a predetermined voltage reference; and

a comparator for receiving the output of the voltage reference circuit and for preventing operation of the gate driver if the supply voltage falls below said predetermined voltage reference.

2. The integrated gate driver circuit of claim 1, wherein all transistors in the circuit are enhancement mode GaN field-effect transistors.

3. The integrated gate driver circuit of claim 2, further comprising the enhancement mode GaN field-effect transistor to be driven.

4. The integrated gate driver circuit of claim 1, wherein the output stage comprises a half bridge circuit formed of a high side enhancement mode GaN transistor and a low side enhancement mode GaN transistor, with the high side enhancement mode GaN transistor inverted relative to the low side enhancement mode GaN transistor.

5. The integrated gate driver circuit of claim 1, further comprising a synchronous bootstrap FET supply gate driver circuit.

6. The integrated gate driver circuit of claim 5, wherein the synchronous bootstrap FET supply gate driver circuit is substantially the same as the gate driver without the output stage.