BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20170352660A1
• Filed: 08/23/2017
• Published: 12/07/2017
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chia-Chung, Huang, Chi-Feng, Liang, Victor Chiang, Tsai, Fu-Huan, Hsieh, Hsieh-Hung, Yeh, Tzu-Jin, Tsai, Han-Min, Chu, Hong-Lin
• Granted Patent: US 10,529,711 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential

Abstract

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Claims

1. A semiconductor device comprising:

one or more fins extending in a first direction over a substrate,

wherein the one or more fins include a first region along the first direction and second regions on either side of the first region along the first direction, and the first region of the fins includes a dopant in a concentration of about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup>, and

the dopant is centered at region in the fin located at about 15 to 20 nm from a top of the fin and 3 to 7 nm in a fin thickness direction from a sidewall extending along the first direction of the fin;

a gate structure overlies the first region of the fins; and

source/drains are formed on the second regions of the fins.

2. The semiconductor device of claim 1, wherein the dopant is an N-type dopant, selected from the group consisting of P, As, and Sb.

3. The semiconductor device of claim 1, wherein the dopant is a P-type dopant, selected from the group consisting of B, BF₂, Al, and Ga.

4. The semiconductor device of claim 1, wherein the concentration of the dopant in the first region is about 1.7×

10¹⁷ to 1.7×

10¹⁹ atoms cm<sup>−

3</sup>.

5. The semiconductor device of claim 4, wherein the concentration of the dopant in the first region is about 1×

10¹⁸ atoms cm<sup>−

3</sup> to 2×

10¹⁸ atoms cm<sup>−

3</sup>.

6. The semiconductor device of claim 1, further comprising a plurality of fins;

and

an isolation insulating layer formed between adjacent fins.

7. The semiconductor device of claim 1, having a gate length between source and drain regions of about 7 nm to about 16 nm.

8. The semiconductor device of claim 1, wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

9. The semiconductor device of claim 1, wherein the source/drain regions are raised source/drain regions.

10. A Gilbert-cell mixer comprising:

a plurality of transistors electrically connected to each other, wherein at least one of the transistors comprises;

one or more fins extending in a first direction over a substrate,

wherein the one or more fins include a first region along the first direction and second regions on either side of the first region along the first direction, and the first region of the fins includes a dopant centered at region in the fin located at about 15 to 20 nm from a top of the fin and 3 to 7 nm in a fin thickness direction from a sidewall extending along the first direction of the fin;

a gate structure overlies the first region of the fins; and

source/drains are formed on the second regions of the fins.

11. The Gilbert-cell mixer of claim 10, wherein the dopant is an N-type dopant selected from the group consisting of P, As, and Sb.

12. The Gilbert-cell mixer of claim 10, wherein the dopant is a P-type dopant selected from the group consisting B, BF₂, Al, and Ga.

13. The Gilbert-cell mixer of claim 10, wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

14. The Gilbert-cell mixer of claim 10, wherein a concentration of the dopant in the first region is about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup>.

15. A buried-channel fin field effect transistor comprising:

one or more fins extending in a first direction over a substrate,

wherein the one or more fins include a channel region along the first direction and source/drain regions on either side of the channel region along the first direction, and the channel region of the fins includes a dopant centered at region in the fin located at about 15 to 20 nm from a top of the fin and 3 to 7 nm in a fin thickness direction from a sidewall extending along the first direction of the fin; and

a gate structure overlies the first region of the fins.

16. The buried-channel fin field effect transistor of claim 15, wherein the dopant is an N-type dopant selected from the group consisting of P, As, and Sb.

17. The buried-channel fin field effect transistor of claim 15, wherein the dopant is a P-type dopant selected from the group consisting B, BF₂, Al, and Ga.

18. The buried-channel fin field transistor of claim 15, wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

19. The buried-channel fin field transistor of claim 15, wherein a concentration of the dopant in the first region is about 1.5×

10¹⁶ to 2.0×

10²⁰ atoms cm<sup>−

3</sup>.

20. The buried-channel fin field transistor of claim 19, wherein the concentration of the dopant in the first region is about 1.7×

10¹⁷ to 1.7×

10¹⁹ atoms cm<sup>−

3</sup>.