TRANSMITTING DATA BETWEEN EXECUTION SLICES OF A MULTI-SLICE PROCESSOR

• US 20170357513A1
• Filed: 06/09/2016
• Published: 12/14/2017
• Est. Priority Date: 06/09/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: AYUB, SALMA, BOWMAN, JOSHUA W., BROWNSCHEIDLE, JEFFREY C., CHADHA, SUNDEEP, JEGANATHAN, DHIVYA, NGUYEN, DUNG Q., SHAH, SALIM A., THOMPTO, BRIAN W.
• Granted Patent: US 10,445,100 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.

Claims

1. A method for transmitting data between execution slices of a multi-slice processor, the method comprising:

receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier;

determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction;

calculating a cycle countdown using the latency and the source identifier;

determining that the cycle countdown has expired; and

in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.

2. The method of claim 1, wherein calculating the cycle countdown using the latency and the source identifier comprises:

obtaining a cycle distance between the execution slice and a location identified by the source identifier, wherein the cycle distance is a number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice;

combining the cycle distance and the latency to obtain the cycle countdown.

3. The method of claim 1, wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown.

4. The method of claim 3, wherein the execution result vector is decremented each cycle by altering the location of the flag corresponding to the value of the cycle countdown.

5. The method of claim 1, wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction.

6. The method of claim 1, wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus.

7. The method of claim 1 further comprising:

using the result data as input for the consumer instruction.

8. A multi-slice computer processor for transmitting data between execution slices of a multi-slice processor, the multi-slice computer processor configured for:

receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier;

determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction;

calculating a cycle countdown using the latency and the source identifier;

determining that the cycle countdown has expired; and

in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.

9. The multi-slice computer processor of claim 8, wherein calculating the cycle countdown using the latency and the source identifier comprises:

obtaining a cycle distance between the execution slice and a location identified by the source identifier, wherein the cycle distance is a number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice;

combining the cycle distance and the latency to obtain the cycle countdown.

10. The multi-slice computer processor of claim 8, wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown.

11. The multi-slice computer processor of claim 10, wherein the execution result vector is decremented each cycle by altering the location of the flag corresponding to the value of the cycle countdown.

12. The multi-slice computer processor of claim 8, wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction.

13. The multi-slice computer processor of claim 8, wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus.

14. The multi-slice computer processor of claim 8, wherein the multi-slice computer processor is further configured for:

using the result data as input for the consumer instruction.

15. A computing system, the computing system including a multi-slice computer processor for transmitting data between execution slices of a multi-slice processor, the multi-slice computer processor configured for:

receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier;

determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction;

calculating a cycle countdown using the latency and the source identifier;

determining that the cycle countdown has expired; and

in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.

16. The computing system of claim 15, wherein calculating the cycle countdown using the latency and the source identifier comprises:

obtaining a cycle distance between the execution slice and a location identified by the source identifier, wherein the cycle distance is a number of cycles required for the result data to travel from the location identified by the source identifier to the execution slice;

combining the cycle distance and the latency to obtain the cycle countdown.

17. The computing system of claim 15, wherein the cycle countdown is stored in an execution result vector by setting a flag corresponding to a value of the cycle countdown.

18. The computing system of claim 17, wherein the execution result vector is decremented each cycle by altering the location of the flag corresponding to the value of the cycle countdown.

19. The computing system of claim 15, wherein determining that the cycle countdown has expired comprises determining that a flag has been set in a ready vector corresponding to the producer instruction.

20. The computing system of claim 15, wherein the result data is transmitted from the source execution slice using a result bus, and wherein reading the result data from the producer instruction comprises reading the result data from the result bus.