MEMORY DEVICE ARCHITECTURE

• US 20170358348A1
• Filed: 08/14/2017
• Published: 12/14/2017
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Castro, Hernan A., Flores, Everardo Torres, Hirst, Jeremy M.
• Granted Patent: US 10,141,051 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Claims

1. (canceled)

2. A system, comprising:

a memory device comprising;

an array of memory cells occupying a footprint; and

a plurality of word line drivers and digit line drivers in a circuit level positioned below the array of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed within the footprint.

3. The system of claim 2, wherein the memory device further comprises interconnects formed in metal levels positioned between the circuit level and the array of memory cells, the interconnects electrically coupling the plurality of word line driver connection points and the digit line driver connection points to the array of memory cells.

4. The system of claim 2, wherein the array of memory cells comprises word lines positioned along a first direction and digit lines positioned along a direction different from the first direction.

5. The system of claim 4, wherein individual memory cells of the array of memory cells are located at intersections of the word lines and the digit lines.

6. The system of claim 4, wherein the word lines are staggered along a word line direction, and the digit lines are staggered along a digit line direction.

7. The system of claim 2, wherein the plurality of word line drivers are each formed within one of a plurality of disjointed word line driver regions distributed across the footprint, and the digit line drivers are each formed within one of a plurality of disjointed digit line driver regions distributed across the footprint.

8. The system of claim 7, wherein each of the plurality of word line driver connection points is centered along a word line direction within one of a plurality of word line driver regions, and each of the digit line driver connection points is centered along a digit line direction within one of a plurality of digit line driver regions.

9. A method, comprising:

forming a memory array of memory cells occupying a footprint; and

forming a plurality of word line drivers in a circuit level, the plurality of word line drivers distributed within the footprint of the memory array; and

forming a plurality of digit line drivers in the circuit level, the plurality of digit line drivers distributed within the footprint of the memory array,

wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed across the footprint.

10. The method of claim 9, further comprising:

forming a plurality of word lines each coupled with and laterally traversing at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.

11. The method of claim 10, wherein each word line driver connection point of the plurality of word line driver connection points is centered along a word line direction within a word line driver region of a plurality of word line driver regions.

12. The method of claim 9, further comprising:

forming a plurality of digit lines each coupled with and laterally traversing at least one of the plurality of digit line drivers at a different vertical level from the plurality of digit line drivers.

13. The method of claim 12, wherein each of the digit line driver connection points is centered along a digit line direction within a digit line driver region of a plurality of digit line driver regions.

14. The method of claim 9, wherein at least two word line drivers of the plurality of word line drivers are positioned along a first direction and at least two digit line drivers of the plurality of digit line drivers are positioned along a second direction orthogonal to the first direction.

15. The method of claim 9, wherein the memory array of memory cells comprises at least two word lines positioned along a first direction and at least two digit lines positioned along a second direction orthogonal to the first direction.

16. The method of claim 15, wherein at least one memory cell of the memory array is located at an intersection of a word line and a digit line.

17. The method of claim 9, wherein forming the plurality of word line drivers and the plurality of digit line drivers comprises:

distributing the plurality of word line drivers and the plurality of digit line drivers across the footprint of the memory array in disjointed word line driver regions and disjointed digit line driver regions.

18. The method of claim 15, wherein word line electrodes connecting the plurality of word line drivers to memory cells of the memory array are staggered relative to one another, and digit line electrodes connecting the plurality of digit line drivers to the memory cells of the memory array are staggered relative to one another.

19. A device, comprising:

a plurality of memory cells within a footprint of the device; and

a plurality of word line drivers and digit line drivers in a circuit level positioned below the plurality of memory cells, wherein the circuit level comprise a plurality of word line driver connection points and digit line driver connection points distributed within the footprint.

20. The device of claim 19, wherein the plurality of word line drivers are distributed across and within the footprint in a plurality of word line driver regions, and wherein the plurality of digit line drivers are distributed across and within the footprint in a plurality of digit line driver regions.

21. The device of claim 19, wherein the plurality of memory cells comprises word lines positioned along a first direction and digit lines positioned along a second direction different from the first direction.