SEMICONDUCTOR DEVICE

• US 20170358676A1
• Filed: 08/08/2017
• Published: 12/14/2017
• Est. Priority Date: 10/16/2014
• Status: Active Application

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: HONG, ZHONGSHAN
• Application Number:
  US15/671,296
• Publication Number:
  US 20170358676A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

Claims

1-16. -16. (canceled).

17. A semiconductor device, comprising:

a stacked substrate, including a substrate, an insulating layer on a surface of the substrate, and a semiconductor layer on a surface of the insulating layer,

wherein the semiconductor layer includes a plurality of first openings therein to expose the insulating layer and to provide a first distance between adjacent sidewalls of adjacent first openings, and

wherein the stacked substrate further includes a plurality of second openings located through the insulating layer and into the substrate at a bottom of the plurality of first openings, and wherein sidewalls of the substrate in the plurality of second openings are recessed with respect to sidewalls of the semiconductor layer in the plurality of first openings, and a second distance is defined between adjacent substrate sidewalls of adjacent second openings, the second distance being shorter than the first distance;

an isolation layer located in the plurality of second openings and the plurality of first openings, wherein a width of the isolation layer in the substrate is greater than a width of the isolation layer in the semiconductor layer;

a gate structure on a surface portion of the semiconductor layer between adjacent isolation layers; and

conductive structures on surface portions of the semiconductor layer on both sides of the gate structure, wherein the conductive structures penetrate through the isolation layer and into the substrate of the stacked substrate.

18. The device according to claim 17, wherein:

the stacked substrate is a semiconductor-on-insulator substrate having an ultra-thin body as the semiconductor layer and a buried oxide as the insulating layer of the stacked substrate,

the semiconductor layer has a thickness between about 5 Å and

about 20 Å

, and

the insulating layer has a thickness between about 5 Å and

about 40 Å

.

19. The device according to claim 17, wherein:

the conductive structures have a bottom part located on a surface of the isolation layer or inside the isolation layer, and

the bottom part of the conductive structures penetrate through the isolating layer of the stacked substrate and into a top surface of the substrate.

20. The device according to claim 17, further including spacers on the sidewall surfaces of the semiconductor layer in the first openings.

21. The device according to claim 20, wherein the spacers are made of a material including one or more of silicon oxide, silicon nitride, silicon oxynitride, polysilicon, and amorphous carbon.

22. The device according to claim 17, wherein the width of the isolation layer in the semiconductor layer is greater than a width of the isolation layer in the insulating layer.

23. The device according to claim 17, further including:

a source region and a drain region in the semiconductor layer on both sides of the gate structure, wherein the conductive structures are located on the source region and the drain region.

24. The device according to claim 23, further including:

a dielectric layer on the isolation layer, the semiconductor layer and the gate structure;

wherein the conductive structures are through the dielectric layer and on the surface portions of the semiconductor layer on both sides of the gate structure.

25. The device according to claim 17, wherein a bottom part of the conductive structures is located on a surface of the isolation layer or inside the isolation layer.

26. The device according to claim 17, wherein a bottom part of the conductive structures extend into the isolation layer and under a top surface of the substrate.