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Semiconductor Chip and Method for Manufacturing the Same

  • US 20170365620A1
  • Filed: 09/06/2017
  • Published: 12/21/2017
  • Est. Priority Date: 03/09/2006
  • Status: Active Grant
First Claim
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1. A semiconductor chip, comprising:

  • gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by an as-fabricated gate pitch of less than or equal to about 193 nanometers, each gate structure layout shape having a substantially rectangular shape and having an as-fabricated gate structure width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along a corresponding gate gridline, wherein each gate gridline has at least one gate structure layout shape positioned thereon, wherein each pair of gate structure layout shapes that are adjacently positioned on a same gate gridline are separated from each other by an as-fabricated line end-to-line end gap of less than or equal to about 193 nanometers;

    a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one dielectric material, adjacent metal layers in the stack of metal layers separated by at least one dielectric material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on a corresponding first-metal gridline, each first-metal structure layout shape having at least one adjacent first-metal structure layout shape positioned next to each of its sides at an as-fabricated y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structure layout shapes that are adjacently positioned on a same first-metal gridline are separated by an as-fabricated line end-to-line end gap of less than or equal to about 193 nanometers;

    at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit.

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