PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

• US 20170373697A1
• Filed: 01/22/2016
• Published: 12/28/2017
• Est. Priority Date: 01/24/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: SCHOBER, Susan Marya, SCHOBER, Robert C., SHAPIRO, Herbert M
• Granted Patent: US 10,439,624 B2
• Time in Patent Office: Days
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/10 Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
• CPC Class Codes: H03L 7/04 wherein the frequency-determining element comprises distributed inductance and capacitance
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

Claims

1. A phase locked loop comprising:

a. a phase frequency detector for detecting differences in phase and frequency between reference signal and feedback signal, and for outputting error signals for causing a charge pump to be in one of idle mode, pump up mode and pump down mode;

b. said charge pump comprising

i. a charge pump capacitor, and

ii. a plurality of switches operable in response to said error signals from said phase frequency detector for causing said charge pump capacitor to be charged from a supply voltage during said idle mode, to discharge from said charge pump capacitor to raise output voltage of said charge pump during said pump up mode, and discharging from said charge pump capacitor to lower output voltage of said charge pump during said pump down mode;

c. a tunable inductor free voltage controlled oscillator, receiving said output voltage from said charge pump as control voltage for increasing or decreasing frequency of said feedback signal of said voltage controlled oscillator.

2. The phase locked loop according to claim 1, wherein said voltage controlled oscillator comprises a phase-injection-locked voltage controlled oscillator.

3. The phase locked loop according to claim 1, wherein said feedback signal is a sine wave signal.

4. The phase locked loop according to claim 1, wherein said said voltage controlled oscillator comprises:

an odd number stages of two or more rings, each of said rings comprising a current starved invertor having input terminal and output terminal,

wherein each stage of said odd number stages comprising first and second capacitors, said first capacitor is capacitively coupling said input terminal of said current starved inverter of a first one of said two or more rings with said output terminal of said current starved inverter of a subsequent one of said two or more rings; and

said second capacitor is capacitively coupling said output terminal of said current starved inverter of said first one of said two or more rings with said input terminal of said current starved inverter of said subsequent one of said two or more rings.

5. The phase locked loop according to claim 4, wherein the layout of said voltage controlled oscillator is symmetric by placing said first and second capacitors in the center of said layout, and placing said odd number of two or more rings symmetrically around the center.

6. The phase locked loop according to claim 1, wherein the phase frequency detector comprises:

a first and second D-flip flops, each comprising input terminal, first and second reset terminals, and first and second output terminals, wherein said first DFF receives said reference signal and said second DFF receives said feedback signal;

wherein said first reset terminal of said first DDF and said second reset terminal of said second DFF are in communication with said second output terminal of said second DFF, and

said second rest terminal of said first DFF and said first reset terminal of said second DFF are in communication with said second output of said first DFF;

said second output terminal of said first DFF is invert of said first output terminal of said first DFF; and

said second output terminal of said second DFF is invert of said first output terminal of said second DFF.

7. The phase locked loop according to claim 1 further comprises a loop filter between said charge pump and voltage controlled oscillator.

8. A phase frequency detector for a phase locked loop for producing error signals for defining at least three modes, comprising:

a first and second dual reset D-flip flops (DFF), each comprising input terminal, first and second reset terminals, and first and second output terminals, wherein said first DFF receives a reference signal and said second DFF receives a feedback signal;

wherein said first reset terminal of said first DDF and said second reset terminal of said second DFF are in communication with said second output terminal of said second DFF, and

said second rest terminal of said first DFF and said first reset terminal of said second DFF are in communication with said second output of said first DFF;

said second output terminal of said first DFF is invert of said first output terminal of said first DFF; and

said second output terminal of said second DFF is invert of said first output terminal of said second DFF.

9. A voltage controlled oscillator for a phase locked loop, comprising:

a. an odd number stages of two or more rings, each of said rings comprising a current starved invertor having input terminal and output terminal,

wherein each stage of said odd number stages comprising first and second capacitors, said first capacitor is capacitively coupling said input terminal of said current starved inverter of a first one of said two or more rings with said output terminal of said current starved inverter of a subsequent one of said two or more rings; and

said second capacitor is capacitively coupling said output terminal of said current starved inverter of said first one of said two or more rings with said input terminal of said current starved inverter of said subsequent one of said two or more rings.

10. The voltage controlled oscillator as recited in claim 9, wherein said current starved inverter comprises complementary injection field effect transistor (CiFET).