SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SIC EPITAXIAL WAFER

• US 20180016706A1
• Filed: 02/16/2016
• Published: 01/18/2018
• Est. Priority Date: 03/03/2015
• Status: Active Grant

• Current Assignee: Resonac Corp. (Resonac Holdings Corp.)
• Original Assignee: Showa Denko KK
• Inventors: NORIMATSU, Jun, MIYASAKA, Akira, KAGESHIMA, Yoshiaki, KAMEI, Koji, MUTO, Daisuke
• Granted Patent: US 10,865,500 B2
• Time in Patent Office: Days
• CPC Class Codes: C30B 25/165 the flow of the reactive gases
• CPC Class Codes: C30B 25/186 being specially pre-treated by, e.g. chemical or physical means
• CPC Class Codes: C30B 25/20 the substrate being of the same materials as the epitaxial layer
• CPC Class Codes: C30B 29/36 Carbides
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 21/2003 characterised by the substrate

Abstract

An SiC epitaxial wafer having an SiC epitaxial layer formed on an SiC single crystal substrate having an offset angle of 4 degrees or less in a <11-20> direction from a (0001) plane. A trapezoidal defect included in the SiC epitaxial wafer includes an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow. Also disclosed is a method for manufacturing the SiC epitaxial wafer.

Claims

1. An SiC epitaxial wafer comprising an SiC epitaxial layer formed on an SiC single crystal substrate having an offset angle of 4 degrees or less in a <

11-20>

direction from a (0001) plane,

wherein a trapezoidal defect included in the SiC epitaxial wafer comprises an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow.

2. The SiC epitaxial wafer according to claim 1, wherein a ratio of the inverted trapezoidal defect in the trapezoidal defect is 50% or more.

3. The SiC epitaxial wafer according to claim 1, wherein the inverted trapezoidal defect comprises an inverted trapezoidal defect having a length of the lower base on the downstream side of the step flow of 0 and a triangular shape.

4. A method for manufacturing an SiC epitaxial wafer which is a method for manufacturing the SiC epitaxial wafer according to claim 1, the method comprising:

an etching step for etching an SiC single crystal substrate; and

an epitaxial growth step for growing an epitaxial layer on the SiC single crystal substrate after etching,

wherein in the epitaxial growth step, a concentration ratio C/Si of a Si-based source gas and a C-based source gas is set to 1.0 or less.

5. The method for manufacturing an SiC epitaxial wafer according to claim 4, wherein a temperature in the epitaxial growth step is set to 1,630°

C. or less.

6. The method for manufacturing an SiC epitaxial wafer according to claim 4, wherein in the etching step, an etching gas is a silane (SiH₄) gas.

7. The method for manufacturing an SiC epitaxial wafer according to claim 4, wherein a temperature in the etching step is lower than a temperature in the epitaxial growth step.