METHOD OF MEASURING MISALIGNMENT OF CHIPS, A METHOD OF FABRICATING A FAN-OUT PANEL LEVEL PACKAGE USING THE SAME, AND A FAN-OUT PANEL LEVEL PACKAGE FABRICATED THEREBY

• US 20180025949A1
• Filed: 05/02/2017
• Published: 01/25/2018
• Est. Priority Date: 07/20/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SOHN, Younghoon, YANG, Yusin
• Granted Patent: US 10,720,365 B2
• Time in Patent Office: Days
• CPC Class Codes: G01B 11/272 using photoelectric detection means
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24101 Connecting bonding areas at the same height
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/25171 Fan-out arrangements
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/8213 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier

Abstract

A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.

Claims

1. A method of measuring misalignment of chips in a substrate, comprising:

obtaining images by scanning the substrate and the chips, the chips being arranged in first and second directions in the substrate, the chips including first to n-th chips arranged in the first direction or the second direction;

obtaining absolute offsets of reference chips with respect to the substrate in the images, the reference chips corresponding to k-th ones of the chips in the images and k being an integer greater than or equal to 1 and less than or equal to n;

obtaining relative offsets of subordinate chips with respect to the reference chips in the images, the subordinate chips corresponding to the chips that are not reference chips among the chips; and

calculating misalignments of the chips based on the absolute offsets and the relative offsets.

2. The method of claim 1, wherein

the obtaining of the image includes scanning the chips in the first direction to obtain traverse images and scanning the chips in the second direction to obtain longitudinal images,

the reference chips in the traverse images are traverse reference chips, which are arranged to form a reference column in the second direction,

the subordinate chips in the traverse images are traverse subordinate chips, which are arranged to form columns other than the reference column,

the reference chips in the longitudinal images are longitudinal reference chips, which are arranged to form a reference row in the first direction, and

the subordinate chips in the longitudinal images are longitudinal subordinate chips, which are arranged to form rows other than the reference row.

3. The method of claim 2, wherein the obtaining the absolute offsets includes:

obtaining absolute vertical offsets of the traverse reference chips with respect to the substrate, in the traverse images; and

obtaining absolute horizontal offsets of the longitudinal reference chips with respect to the substrate, in the longitudinal images.

4. The method of claim 3, wherein the obtaining the relative offsets includes:

obtaining relative vertical offsets of the traverse subordinate chips with respect to the traverse reference chips, in the traverse images, and

obtaining relative horizontal offsets of the longitudinal subordinate chips with respect to the longitudinal reference chips, in the longitudinal images.

5. The method of claim 4, wherein the calculating misalignments of the chips includes calculating vertical misalignments of the chips in the second direction and calculating horizontal misalignments of the chips in the first direction.

6. The method of claim 5, wherein the calculating the vertical misalignments includes calculating the vertical misalignments based on a sum of the absolute vertical offsets and the relative vertical offsets.

7. The method of claim 5, wherein the calculating the horizontal misalignments includes calculating the horizontal misalignments based on a sum of the absolute horizontal offsets and the relative horizontal offsets.

8. The method of claim 3, wherein the obtaining absolute vertical offsets includes obtaining the absolute vertical offsets based on differences between measured vertical distances of the traverse reference chips with respect to the substrate and reference vertical distances.

9. The method of claim 3, wherein the obtaining absolute horizontal offsets includes obtaining the absolute horizontal offsets based on differences between measured horizontal distances of the longitudinal reference chips with respect to the substrate and reference horizontal distances.

10. The method of claim 2, wherein

the reference column of the second direction corresponds to a first one of the longitudinal images, and

the reference row of the first direction corresponds to a first one of the traverse images.

11. A method of fabricating a package, comprising:

forming cavities in a substrate;

applying an adhesive tape to the substrate;

providing chips in the cavity and on the adhesive tape, the chips being arranged in first and second directions in the substrate, the chips including first to n-th chips arranged in the first direction or the second direction;

forming an encapsulation layer on the substrate, the chips, and the adhesive tape;

removing the adhesive tape; and

measuring misalignments of the chips with respect to the substrate, the measuring the misalignments of the chips including,

obtaining images by scanning the substrate and chips provided in the substrate,

obtaining absolute offsets of reference chips with respect to the substrate in the images, the reference chips corresponding to k-th ones of the chips in the images and k being an integer greater than or equal to 1 and less than or equal to n,

obtaining relative offsets of subordinate chips with respect to the reference chips in the images, the subordinate chips corresponding to the chips that are not reference chips among the chips, and

calculating misalignments of the chips based on the absolute offsets and the relative offsets.

12. The method of claim 11, further comprising:

forming an insulating layer on the substrate and the chips; and

forming first contact holes in the insulating layer, wherein

the forming the first contact holes includes providing light to a portion of the insulating layer on device pads of the chips, based on the misalignments of the chips.

13. The method of claim 12, wherein the forming the first contact hole further includes providing light to a portion of the insulating layer on substrate pads of the substrate, based on substrate alignment marks of the substrate.

14. The method of claim 13, further comprising:

forming lines on the insulating layer to connect the substrate to the chips,

wherein the forming the lines includes forming a seed metal layer on the substrate, forming photoresist patterns on the seed metal layer by performing a photolithography process based on the misalignment of the chips, and forming metal line layers on the seed metal layer between the photoresist patterns.

15. The method of claim 14, wherein the forming of the photoresist patterns includes:

forming a photoresist layer on the insulating layer;

providing light to a portion of the photoresist layer from substrate pads of the substrate to sidewalls of the chips in the cavities, based on the substrate alignment marks; and

providing light to a portion of the photoresist layer from device pads of the chips to sidewalls of the substrate in the cavities, based on the misalignments of the chips.

16-20. -20. (canceled)

21. A method of measuring misalignment of chips in a substrate, comprising:

obtaining an image of the chips on the substrate, the chips being spaced apart from each other in rows and columns in the substrate, the chips including chip alignment marks, the substrate including substrate alignment marks corresponding to the chip alignment marks;

obtaining absolute vertical offsets of traverse reference chips with respect to the substrate in the images, the traverse reference chips corresponding to a selected chip from each of the rows of chips, the absolute vertical offsets being based on vertical distance reference values and distances between the chip alignment marks of the traverse reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the traverse reference chips;

obtaining relative vertical offsets of first subordinate reference chips with respect to the traverse reference chips in the images, the first subordinate chips corresponding to unselected chips from each of the rows of chips, the relative vertical offsets being based on distances between the chip alignment marks of the traverse reference chips and the chip alignment marks of the first subordinate chips that are adjacent to the chip alignment marks of the traverse reference chips;

obtaining absolute horizontal offsets of longitudinal reference chips with respect to the substrate in the images, the longitudinal reference chips corresponding to a selected chip from each of the columns of chips, the absolute horizontal offsets being based on horizontal distance reference values and distances between the chip alignment marks of the longitudinal reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the longitudinal reference chips;

obtaining relative horizontal offsets of second subordinate reference chips with respect to the longitudinal reference chips in the images, the second subordinate chips corresponding to unselected chips from each of the columns of chips, the horizontal vertical offsets being based on the absolute horizontal offsets and distances between the chip alignment marks of the longitudinal reference chips and the chip alignment marks of the second subordinate chips that are adjacent to the chip alignment marks of the longitudinal reference chips; and

calculating misalignments of the chips based on the absolute vertical offsets, absolute horizontal offsets, relative vertical offsets, and relative horizontal offsets.

22. The method of claim 21, wherein

the obtaining absolute vertical offsets is performed before the obtaining absolute horizontal vertical offsets,

the traverse reference chips are all in a selected one of the columns of chips,

the first subordinate reference chips are from unselected columns of the chips,

the longitudinal reference chips are all in a selected one of the rows of chips, and

the second subordinate reference chips are from unselected rows of the chips.

23. The method of claim 21, wherein

the obtaining relative vertical offsets is performed before the obtaining absolute vertical offsets,

the traverse reference chips are all in a selected one of the columns of chips,

the first subordinate reference chips are from unselected columns of the chips,

the longitudinal reference chips are all in a selected one of the rows of chips, and

the second subordinate reference chips are from unselected rows of the chips.

24. The method of claim 21, wherein

the obtaining absolute vertical offsets of traverse reference chips includes determining the absolute vertical offsets based on a difference between the vertical distance reference values and vertical distances between the chip alignment marks of the traverse reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the traverse reference chips, and

the obtaining absolute horizontal offsets of longitudinal reference chips includes determining the absolute horizontal offsets based on a difference between the horizontal distance reference values and horizontal distances between the chip alignment marks of the longitudinal reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the longitudinal reference chips.

25. A method of fabricating a package, comprising:

forming chips in a substrate, the chips being spaced apart from each other in rows and columns in the substrate, the chips including chip alignment marks, the substrate including substrate alignment marks corresponding to the chip alignment marks;

forming an encapsulation layer on the chips in the substrate;

measuring misalignments of the chips in the substrate using the method of claim 21;

forming an insulating layer on the substrate and the chips; and

forming first contact holes in the insulating layer, wherein

the forming the first contact holes includes providing light to a portion of the insulating layer on the chips, based on the misalignments of the chips in the substrate.