Measuring Internal Signals of an Integrated Circuit

• US 20180038913A1
• Filed: 10/19/2017
• Published: 02/08/2018
• Est. Priority Date: 02/11/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Murthy, Kushal D, Parmar, Manish, Tadeparthy, Preetam, Venkateswaran, Muthusubramanian
• Granted Patent: US 10,459,030 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Claims

1. A device comprising:

one or more blocks of circuitry;

a multiplexor having a plurality of inputs and an output;

a plurality of internal signal lines coupled from the one or more blocks of circuitry to respective ones of the plurality of inputs on the multiplexor;

a buffer with an input coupled to the output of the multiplexor and an output selectively coupled to a first external pin of the device; and

a direct signal line configured to selectively couple the output of the multiplexor directly to the first external pin of the device, such that the buffer is bypassed.

2. The device of claim 1, further including a second external pin on the device coupled to one of the plurality of inputs of the multiplexor.

3. The device of claim 1, in which the buffer is a unity gain buffer.

4. The device of claim 1, in which one or more additional buffers are selectively coupled between the output of the multiplexor and the first external pin.

5. The device of claim 4, in which a first one of the buffers is a PMOS source follower, and in which a second one of the buffers is an NMOS source follower, and in which the PMOS source follower is configured for buffering signals having an amplitude in a range of approximately a threshold value to a ground reference value, and in which the NMOS source follower is configured for buffering signals having an amplitude in a range of approximately a threshold value to a supply reference value.

6. The device of claim 1, in which only internal signals that are connected to the multiplexor are coupled to the first external pin.

7. An integrated circuit comprising:

functional logic having a plurality of internal signal lines; and

test logic with a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit (IC), in which the test logic includes a buffer, and in which the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC.

8. The integrated circuit of claim 7, further including a second external pin coupled to an input of the test logic, in which the test logic is configured to selectively couple a signal received on the second external pin of the IC via the buffer to the first external pin of the IC.

9. The device of claim 7, in which the buffer is a unity gain buffer.

10. The device of claim 7, in which the test logic includes one or more additional buffers, and in which the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the one or more additional buffers to the first external pin of the IC.

11. The device of claim 10, in which a first one of the buffers is a PMOS source follower, and in which a second one of the buffers is an NMOS source follower.

12. The device of claim 11, in which the PMOS source follower is configured for buffering signals having an amplitude in a range of approximately a threshold value to a ground reference value, and in which the NMOS source follower is configured for buffering signals having an amplitude in a range of approximately a threshold value to a supply reference value.