Mechanism to Accelerate Graphics Workloads in a Multi-Core Computing Architecture

• US 20180040096A1
• Filed: 08/05/2016
• Published: 02/08/2018
• Est. Priority Date: 08/05/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Benthin, Carsten, Woop, Sven, Wald, Ingo
• Granted Patent: US 10,229,470 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Claims

1. A processor comprising:

a first processing core of a processor coupled to an internal cache of the processor as a direct agent for thread instructions and data; and

a second processing core of the processor coupled to the cache as a direct agent for separate thread instructions and data;

a first programmable integrated circuit (IC) of the processor coupled to the first processing core to execute workloads assigned by the first processing core and coupled to the cache as a direct agent to access data of the first processing core independent of the first processing core to independently execute workloads; and

a second programmable IC of the processor coupled to the second processing core to execute workloads assigned by the second processing core and coupled to the cache as a direct agent to access data of the second processing core independent of the second processing core to independently execute workloads.

2. The apparatus of claim 1, wherein the first and second programmable ICs are field programmable gate arrays (FPGAs) that accelerate execution of performance critical loops in a workload.

3. The apparatus of claim 2, wherein the first processing core selects a first workload to be accelerated at the first programmable IC and the second processing core selects a second workload to be accelerated at the second programmable IC.

4. The apparatus of claim 2, wherein the first programmable IC is programmed to execute a first type of workload and the second programmable IC is programmed to execute a second type of workload.

5. The apparatus of claim 2, wherein the first and second programmable ICs provide one or more independent threads to perform latency hiding.

6. The apparatus of claim 2, wherein the first processing core comprises a first controller to control execution of the first programmable IC, and the second processing core comprises a second controller to control execution of the second programmable IC.

7. The apparatus of claim 6, wherein the first controller and the second controller control execution of the first programmable IC and the second programmable IC via memory-mapped I/O (MMIO) regions.

8. The apparatus of claim 6, wherein the first controller and the second controller control execution of the first programmable IC and the second programmable IC via dedicated processor instructions.

9. The apparatus of claim 2, wherein the processing apparatus comprises a general-purpose microprocessor.

10. The apparatus of claim 9, wherein the cache comprises:

a first cache memory device coupled to the first processing core and the first programmable IC; and

a second cache memory device coupled to the second processing core and the second programmable IC.

11. The apparatus of claim 10, wherein the first programmable IC is an independent agent to the first cache memory device, and the second programmable IC is an independent agent to the second cache memory device.

12. The apparatus of claim 9, further comprising:

a third processing core coupled to the first programmable IC; and

wherein the cache comprises a first cache memory device coupled only to the first processing core, the third processing core and the first programmable IC, wherein the first programmable IC accelerates execution of workloads processed at the first processing core and the third processing core.

13. The apparatus of claim 2, wherein the processing apparatus comprises a graphics processing unit (GPU).

14. The apparatus of claim 13, wherein the cache comprises:

a first memory device coupled to the first processing core and the first programmable IC; and

a second memory device coupled to the second processing core and the second programmable IC.

15. The apparatus of claim 13, further comprising:

a third processing core coupled to the first programmable IC; and

wherein the cache comprises a first memory device coupled only to the first processing core, the third processing core and the first programmable IC, wherein the first programmable IC accelerates execution of workloads processed at the first processing core and the third processing core.

16. A central processing unit (CPU), comprising:

a plurality of processing cores including a first processing and a second processing core;

a first field programmable gate array (FPGA) of the CPU coupled to the first processing core to execute workloads assigned by the first processing core;

a first cache memory device of the CPU coupled to the first processing core and the first FPGA, wherein the first processing core and the first FPGA are independently coupled to the first cache memory device as direct agents for independent access to thread instructions and data;

a second FPGA of the CPU coupled to the second processing core execute workloads assigned by the second processing core; and

a second cache memory device of the CPU coupled to the second processing core and the second FPGA, wherein the second processing core and the second FPGA are independently coupled to the second cache memory device as direct agents for independent access to thread instructions and data.

17. The CPU of claim 16, wherein the first processing core selects a first workload to be accelerated at the first FPGA and the second processing core selects a second workload to be accelerated at the second FPGA.

18. The CPU of claim 17, wherein the first FPGA is programmed to execute a first type of workload and the second FPGA is programmed to execute a second type of workload.

19. The CPU of claim 18, wherein the first processing core comprises a first controller to control execution of the first FPGA, and the second processing core comprises a second controller to control execution of the second FPGA.

20. The CPU of claim 16, further comprising a third processing core coupled to the first FPGA and the first cache memory device, wherein the first FPGA accelerates execution of workloads processed at the first processing core and the third processing core.

21. A graphics processing unit (GPU), comprising:

a plurality of graphics processing cores of the GPU, including a first graphics processing core and a second graphics processing core;

a first field programmable gate array (FPGA) of the GPU coupled to the first graphics processing core to execute workloads assigned by the first graphics processing core;

a first memory device coupled to the first graphics processing core and the first FPGA, wherein the first processing core and the first FPGA are independently coupled to the first memory device as direct agents for independent access to thread instructions and data;

a second FPGA of the GPU coupled to the second graphics processing core to execute workloads assigned by the second graphics processing core; and

a second memory device coupled to the second graphics processing core and the second FPGA, wherein the second processing core and the second FPGA are independently coupled to the second memory device as direct agents for independent access to thread instructions and data.

22. The GPU of claim 21, wherein the first graphics processing core selects a first workload to be accelerated at the first FPGA and the second graphics processing core selects a second workload to be accelerated at the second FPGA.

23. The GPU of claim 22, wherein the first FPGA is programmed to execute a first type of graphics workload and the second FPGA is programmed to execute a second type of graphics workload.

24. The GPU of claim 23, wherein the first graphics processing core comprises a first controller to control execution of the first FPGA, and the second graphics processing core comprises a second controller to control execution of the second FPGA.

25. The GPU of claim 21, further comprising a third graphics processing core coupled to the first FPGA and the first memory device, wherein the first FPGA accelerates execution of workloads processed at the first graphics processing core and the third graphics processing core.