SEMICONDUCTOR DEVICE COMPRISING A TRANSISTOR CELL INCLUDING A SOURCE CONTACT IN A TRENCH, METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT

• US 20180040729A1
• Filed: 10/17/2017
• Published: 02/08/2018
• Est. Priority Date: 08/14/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Dresden GmbH (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Dresden GmbH (Infineon Technologies AG)
• Inventors: MEISER, Andreas, GEBHARDT, Karl-Heinz, SCHLOESSER, Till, WEBER, Detlef
• Granted Patent: US 10,381,475 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/223 using diffusion into or out of a solid from or into a gaseous phase H01L21/221 - H01L21/222 take precedence; diffusion through an applied layer H01L21/225
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

Claims

1. A method of manufacturing a semiconductor device comprising a transistor cell in a semiconductor substrate having a first main surface, the method comprising:

forming a source region;

forming a source contact electrically connected to the source region;

forming a drain region;

forming a body region; and

forming a gate electrode in a gate trench, the gate electrode being configured to control a conductivity of a channel formed in the body region,

the source region, the body region and the drain region being disposed along a first direction, the first direction being parallel to the first main surface,

forming the source contact comprises forming a source contact groove in the first main surface of the semiconductor substrate to a depth larger than a depth of the gate trench; and

performing a doping process to introduce dopants of a second conductivity type through a first portion of a sidewall of the source contact groove and to introduce dopants of a first conductivity type through a second portion of the sidewall of the source contact groove.

2. The method according to claim 1, wherein performing the doping process comprises:

forming a diffusion material layer on a sidewall and a bottom side of the source contact groove;

patterning the diffusion material layer to uncover portions of the sidewall;

introducing dopants of the second conductivity type through the uncovered portions of the sidewall; and

performing a heat treatment to introduce dopants of the first conductivity type through covered portions of the sidewall.

3. The method according to claim 2, wherein patterning the diffusion material layer is performed so as to uncover upper portions of the sidewall while leaving lower portions of the sidewall covered.

4. The method according to claim 1, further comprising:

forming a drain contact groove to form a drain contact electrically connected to the drain region.

5. The method according to claim 4, wherein forming the source contact groove and forming the drain contact groove comprises joint etching processes.

6. The method according to claim 1, wherein the source region is formed at the first portion of the sidewall of the source contact groove by the doping process.

7. The method according to claim 1, wherein:

forming the source region includes the doping process to introduce the dopants of the second conductivity type through the first portion of the sidewall of the source contact groove such that the source region is formed at the first portion of the sidewall of the source contact groove.

8. The method according to claim 1, wherein a doped layer is formed at the second portion of the sidewall of the source contact groove by the doping process to introduce the dopants of the first conductivity type through the second portion of the sidewall of the source contact groove.

9. The method according to claim 1, further comprising:

forming a drain contact electrically connected to the drain region, the drain contact being disposed in a drain contact groove.

10. The method according to claim 1, wherein:

forming the source contact comprises forming a first source contact portion and a second source contact portion, the second source contact portion being disposed at a second main surface of the semiconductor substrate.

11. The method according to claim 10, wherein:

forming the first source contact portion comprises filling the source contact groove with a source conductive material such that the source conductive material is in direct contact with the source region, wherein the source conductive material extends partially into a first doped portion of the semiconductor substrate, and wherein the first doped portion includes a region arranged between the source conductive material and the second source contact portion.

12. The method according to claim 11, further comprising:

forming the semiconductor substrate, comprising forming the first doped portion and a second doped portion having a same conductivity type,

wherein the first doped portion having a larger distance to the first main surface than the second doped portion, the first doped portion having a larger doping concentration than the second doped portion, and the first doped portion being a component of the first source contact portion

13. The method according to claim 12, further comprising:

forming a drain contact electrically connected to the drain region, the drain contact being disposed in a drain contact groove. and wherein the drain contact groove at least partially extends into the second doped portion of the semiconductor substrate.

14. The method according to claim 12, wherein:

forming the first doped portion comprises forming a contact portion in the first doped portion, the contact portion having a higher doping concentration than a remaining part of the first doped portion, and the contact portion formed in contact with the source conductive material.

15. The method according to claim 12, wherein the first doped portion and the second doped portion of the semiconductor substrate are of a first conductivity type, and the source region and the drain region are of a second conductivity type.