Current-controlled CMOS logic family

• US 20180048298A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 06/28/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP (Singapore) PTE Limited (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Granted Patent: US 10,396,763 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to;

receive a plurality of signals; and

process the plurality of signals to generate a signal.

2. The apparatus of claim 1 further comprising:

CMOS circuitry, within the integrated circuit, configured to;

receive the plurality of signals; and

process the plurality of signals to generate another plurality of signals; and

C³MOS circuitry, within the integrated circuit, configured to;

receive the another plurality of signals from the CMOS circuitry; and

process the another plurality of signals to generate the signal.

3. The apparatus of claim 1, wherein:

each of the plurality of signals has a first frequency; and

the signal is a serialized signal that is based on the plurality of signals and has a second frequency that is different than the first frequency.

4. The apparatus of claim 1, wherein at least one of the plurality of signals or the signal including data compliant with a fiber channel.

5. The apparatus of claim 1, wherein the C³MOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

6. The apparatus of claim 1 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

7. The apparatus of claim 1, wherein:

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with at least one of receiving the plurality of signals or processing the plurality of signals to generate the signal.

8. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to;

receive a signal; and

process the signal to generate a plurality of signals.

9. The apparatus of claim 8 further comprising:

CMOS circuitry, within the integrated circuit, configured to;

receive the signal; and

process the signal to generate another plurality of signals;

CMOS circuitry, within the integrated circuit, configured to;

receive the another plurality of signals from the C³MOS circuitry;

process the another plurality of signals to generate the plurality of signals; and

output the plurality of signals.

10. The apparatus of claim 8, wherein:

the signal is a serialized signal that has a first frequency; and

each of the plurality of signals has a second frequency that is different than the first frequency.

11. The apparatus of claim 8, wherein at least one of the signal or the plurality of signals including data compliant with a fiber channel.

12. The apparatus of claim 8, wherein the C³MOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

13. The apparatus of claim 8 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

14. The apparatus of claim 8, wherein:

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with at least one of receiving the signal or processing the signal to generate the plurality of signals.

15. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to;

receive a signal;

process the signal to generate a first plurality of signals; and

process the first plurality of signals to generate a second plurality of signals.

16. The apparatus of claim 15 further comprising:

C³MOS circuitry, within the integrated circuit, configured to;

receive the signal; and

process the signal to generate the first plurality of signals;

first CMOS circuitry, within the integrated circuit, configured to;

receive a first of the first plurality of signals from the C³MOS circuitry;

process the first of the plurality of signals to generate a first of the second plurality of signals; and

output the first of the second plurality of signals; and

second CMOS circuitry, within the integrated circuit, configured to;

receive a second of the first plurality of signals from the C³MOS circuitry;

process the second of the plurality of signals to generate a second of the second plurality of signals; and

output the second of the second plurality of signals.

17. The apparatus of claim 15, wherein:

the signal is a serialized signal that has a first frequency;

each of the first plurality of signals has a second frequency that is different than the first frequency; and

each of the second plurality of signals has the second frequency.

18. The apparatus of claim 15, wherein the C³MOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

19. The apparatus of claim 15 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

20. The apparatus of claim 15, wherein:

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with at least one of receiving the signal, processing the signal to generate the first plurality of signals, or processing the first plurality of signals to generate the second plurality of signals.