Configurable Computing Array Based on Three-Dimensional Vertical Writable Memory

• US 20180048315A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,075,169 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-W_V) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.

Claims

1. A configurable computing array, comprising:

a semiconductor substrate;

at least a configurable logic element formed on said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;

at least a configurable computing element formed above said configurable logic element, wherein said configurable computing element comprises a three-dimensional vertical writable memory (3D-W_V) array for storing at least a portion of a look-up table (LUT) for a math function;

wherein said configurable computing array realizes a math function by programming said configurable logic element and said configurable computing element.

2. The configurable computing array according to claim 1, further comprising at least a configurable interconnect for selectively coupling said configurable computing element and said configurable logic element.

3. The configurable computing array according to claim 1, wherein said 3D-W_V array overlaps at least a portion of said configurable logic element.

4. The configurable computing array according to claim 1, wherein said 3D-W_V array comprises vertical transistors or transistor-like devices.

5. The configurable computing array according to claim 4, wherein said 3D-W_V array comprises 3D-NAND array.

6. The configurable computing array according to claim 1, wherein said 3D-W_V array comprises vertical diodes or diode-like devices.

7. A configurable computing array, comprising:

a semiconductor substrate;

at least a configurable interconnect formed on said semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library;

at least a configurable computing element formed above said configurable interconnect, wherein said configurable computing element comprises a three-dimensional vertical writable memory (3D-W_V) array for storing at least a portion of a look-up table (LUT) for a math function;

wherein said configurable computing array realizes a math function by programming said configurable interconnect and said configurable computing element.

8. The configurable computing array according to claim 7, further comprising at least a configurable logic element formed on said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library.

9. The configurable computing array according to claim 7, wherein said 3D-W_V array overlaps at least a portion of said configurable interconnect.

10. The configurable computing array according to claim 7, wherein said 3D-W_V array comprises vertical transistors or transistor-like devices.

11. The configurable computing array according to claim 10, wherein said 3D-W_V array comprises 3D-NAND array.

12. The configurable computing array according to claim 11, wherein said 3D-W_V array comprises vertical diodes or diode-like devices.

13. A configurable computing array, comprising:

a semiconductor substrate;

at least a configurable interconnect formed on said semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library;

at least a configurable logic element formed on said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;

at least a configurable computing element formed above said configurable interconnect, wherein said configurable computing element comprises a three-dimensional vertical writable memory (3D-W_V) array for storing at least a portion of a look-up table (LUT) for a math function;

wherein said configurable computing array realizes a math function by programming said configurable interconnect, said configurable logic element and said configurable computing element.

14. The configurable computing array according to claim 13, wherein said 3D-W_V array overlaps at least a portion of said configurable interconnect.

15. The configurable computing array according to claim 13, wherein said 3D-W_V array overlaps at least a portion of said configurable logic element.

16. The configurable computing array according to claim 13, wherein said 3D-W_V array comprises vertical transistors or transistor-like devices.

17. The configurable computing array according to claim 13, wherein said 3D-W_V array comprises vertical diodes or diode-like devices.

18. The configurable computing array according to claim 13, wherein said 3D-W_V array is an OTP (one-time-programmable) array.

19. The configurable computing array according to claim 13, wherein said 3D-W_V array is an MTP (multiple-time-programmable) array.

20. The configurable computing array according to claim 13, further comprising at least one multiplier.