METHOD AND SYSTEM FOR HETEROGENEOUS SUBSTRATE BONDING FOR PHOTONIC INTEGRATION

• US 20180052283A1
• Filed: 06/26/2017
• Published: 02/22/2018
• Est. Priority Date: 10/13/2009
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Krasulick, Stephen B., Dallesasse, John
• Granted Patent: US 10,373,939 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12147 Coupler
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/0237 by soldering
• CPC Class Codes: H01S 5/1003 Waveguide having a modified shape along the axis, e.g. branched, curved, tapered, voids

Abstract

A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.

Claims

1. A hybrid integrated optical device comprising:

a substrate;

a first pad, disposed on a first region of the substrate and bonded to the substrate;

a device;

a second pad, disposed on a first region of the device and bonded to the device; and

a bonding metal, wherein;

the bonding metal comprises In_0.7Pd_0.3;

the bonding metal is disposed between the first pad and the second pad;

the bonding metal is bonded to the first pad and the second pad; and

the bonding metal, the first pad, and the second pad secure the device to the substrate.

2. The hybrid integrated optical device of claim 1, wherein:

the first pad comprises at least one of Ti, Cr, Pt, Ni or W; and

the second pad comprises at least one of Ti, Cr, Pt, Ni or W.

3. The hybrid integrated optical device of claim 1, wherein:

the substrate comprises a waveguide; and

the device is a compound semiconductor device that emits light, wherein the light is optically coupled into the waveguide.

4. The hybrid integrated optical device of claim 1, wherein the substrate is a silicon-on-insulator substrate comprising a silicon handle portion, an oxide layer, and a silicon layer.

5. The hybrid integrated optical device of claim 4, wherein a first portion of the silicon layer forms a recess proximate the first pad, and wherein a height of the device exceeds a height of a second portion of the silicon layer.

6. The hybrid integrated optical device of claim 4, wherein a first portion of the silicon layer forms a recess proximate the first pad, and wherein a top surface of the device is coplanar with a second portion of the silicon layer.

7. The hybrid integrated optical device of claim 4, further comprising a planarizing material.

8. The hybrid integrated optical device of claim 7, wherein at least a portion of the planarizing material is removed, and further comprising an interconnect metal that provides electrical connectivity to at least one of the device and the silicon layer, at a location where the portion of the planarizing material is removed.

9. The hybrid integrated optical device of claim 4, wherein:

the first region of the substrate is a first region of the silicon layer;

the bonding metal forms a first bond; and

the substrate and the device form a second bond, the second bond comprising a direct semiconductor/semiconductor bond between a second region of the silicon layer and a second region of the device.

10. The hybrid integrated optical device of claim 9, further comprising a light-emitting device that is operable to emit light through the direct semiconductor/semiconductor bond.

11. The hybrid integrated optical device of claim 10, wherein the light-emitting device comprises a compound semiconductor optical device.

12. The hybrid integrated optical device of claim 10, wherein the light-emitting device is an optical generator.

13. The hybrid integrated optical device of claim 9, wherein light propagates parallel to an interface between the second region of the silicon layer and the second region of the device, such that the light evanescently couples across the direct semiconductor/semiconductor bond, between the silicon layer and the device.

14. The hybrid integrated optical device of claim 4, wherein:

the first region of the substrate is a first region of the silicon layer;

the bonding metal forms a first bond; and

the substrate and the device form a second bond between a second region of the silicon layer and a second region of the device, the second bond comprising a metal-assisted semiconductor/semiconductor bond that includes a metal interface layer having a thickness of less than 100 Å

.

15. The hybrid integrated optical device of claim 14, wherein the metal interface layer comprises InPd.

16. The hybrid integrated optical device of claim 14, wherein the silicon layer is characterized by a first coefficient of thermal expansion (CTE) and the device is characterized by a second CTE, wherein the first CTE and the second CTE are different from one another.

17. The hybrid integrated optical device of claim 14, wherein the substrate and the device form a third bond comprising a direct semiconductor/semiconductor bond between a third region of the silicon layer and a third region of the device.