APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY

• US 20180061471A1
• Filed: 08/16/2017
• Published: 03/01/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kawamura, Christopher J., Derner, Scott J.
• Granted Patent: US 10,127,965 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 11/2297 Power supply circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H10B 53/10 characterised by the top-view layout
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region

Abstract

Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

Claims

1. A method, comprising:

increasing a voltage of a first cell plate of a capacitor to change a voltage of a second cell plate of the capacitor, a second digit line, and a second sense node;

decreasing the voltage of the second cell plate and the second digit line to change the voltage of the first cell plate, a first digit line, and a first sense node;

driving the first sense node to a first voltage and driving the second sense node to a second voltage responsive to the voltage of the first sense node being greater than the voltage of the second sense node; and

driving the first sense node to the second voltage and driving the second sense node to the first voltage responsive to the voltage of the first sense node being less than the voltage of the second sense node.

2. The method of claim 1 wherein the voltage of the first sense node is greater than the voltage of the second sense node when the capacitor has a first polarization, and wherein the voltage of the first sense node is less than the voltage of second sense node when the capacitor has a second polarization different than the first polarization.

3. The method of claim 1, further comprising providing a constant voltage to the second sense node as a reference voltage.

4. The method of claim 3 wherein decreasing the voltage of the second cell plate and the second digit line comprises decreasing the voltage of the second cell plate from the constant voltage to ground.

5. The method of claim 1 wherein the second cell plate of the capacitor changes from an initial voltage to a first increased voltage responsive to increasing the voltage of the first cell plate for a first polarization of the capacitor and wherein the second cell plate of the capacitor changes from the initial voltage to a second increased voltage responsive to increasing the voltage of the first cell plate for a second polarization of the capacitor, the first and second voltages are different.

6. The method of claim 5 wherein decreasing the voltage of the second cell plate and the second digit line comprises decreasing the voltage of the second cell plate from the first or second increased to the initial voltage.

7. A method, comprising:

providing a read voltage to a first digit line and to a first plate of a capacitor coupled to the first digit line to cause a voltage of a second plate of the capacitor, of a second digit line coupled to the second plate of the capacitor, and of a second sense node of a sense component to change from an initial voltage to an increased voltage, the second sense node coupled to the second digit line;

coupling a first sense node of the sense component to the first digit line;

decoupling the second sense node from the second digit line;

driving the voltage of the second digit line and the second plate of the capacitor from the increased voltage to the initial voltage to cause a voltage of the first plate of the capacitor, the first digit line, and the first sense node to change;

comparing at the sense component the voltage of the first sense node to a reference voltage; and

based on the comparison, driving the first sense node, first digit line, and first plate of the capacitor to a first voltage and driving the second sense node, second digit line, and second plate of the capacitor to a second voltage, the second voltage complementary to the first voltage.

8. The method of claim 7, further comprising activating selection components to couple the first plate of the capacitor to the first digit line and to couple the second plate of the capacitor to the second digit line.

9. The method of claim 7, further comprising:

changing the voltage of the first and second plates of the capacitor to a same voltage; and

deactivating selection components to isolate the first plate and the second plate of the capacitor from the first and second digit lines, respectively.

10. The method of claim 7 wherein the initial voltage is ground.

11. The method of claim 7 wherein driving the first sense node, first digit line, and first plate of the capacitor to a first voltage and driving the second sense node, second digit line, and second plate of the capacitor to a second voltage, the second voltage complementary to the first voltage, comprises:

driving the first sense node, first digit line, and first plate of the capacitor to ground and driving the second sense node, second digit line, and second plate of the capacitor to the read voltage responsive to the voltage of the first sense node being less than the reference voltage; and

driving the first sense node, first digit line, and first plate of the capacitor to the read voltage and driving the second sense node, second digit line, and second plate of the capacitor to ground responsive to the voltage of the first sense node being greater than the reference voltage.

12. The method of claim 7 wherein the reference voltage is a constant voltage.

13. The method of claim 7 wherein the reference voltage is a first reference voltage responsive to a first increased voltage and wherein the reference voltage is a second reference voltage that is different than the first reference voltage responsive to a second increased voltage.

14. A method, comprising:

coupling a voltage increase across a capacitor from a first plate to a second plate, a resulting voltage at the second plate provided to a sense component, the resulting voltage at the second plate having a first voltage responsive to the capacitor having a first polarization and having a second voltage responsive to the capacitor having a second polarization;

coupling a voltage decrease across the capacitor from the second plate to the first plate, a resulting voltage at the first plate provided to the sense component; and

latching at the sense component a voltage difference between the resulting voltage at the first plate and a reference voltage.

15. The method of claim 14 wherein the reference voltage is the resulting voltage at the second plate.

16. The method of claim 14 wherein the reference voltage is a constant voltage.

17. The method of claim 14, further comprising:

outputting a first logic value when the resulting voltage at the first plate is greater than the reference voltage; and

outputting a second logic value when the resulting voltage at the first plate is less than the reference voltage.

18. The method of claim 14 wherein coupling a voltage decrease across the capacitor from the second plate to the first plate comprises driving the second plate from the resulting voltage at the second plate to ground.

19. The method of claim 14 wherein coupling a voltage increase across a capacitor from a first plate to a second plate comprises driving the first plate from ground to a read voltage.

20. The method of claim 14 wherein latching at the sense component a voltage difference between the resulting voltage at the first plate and the reference voltage comprises:

detecting the voltage difference between the resulting voltage at the first plate and the reference voltage; and

amplifying the voltage difference between the resulting voltage at the first plate reference voltage.

21. The method of claim 14, further comprising restoring the polarization of the capacitor with the latched voltages.

22. A method, comprising:

providing a read voltage to a first plate of a ferroelectric memory cell to change a voltage on a second plate of the ferroelectric memory cell;

driving the second plate of the ferroelectric memory cell to ground to change a voltage on the first plate of the ferroelectric memory cell;

after driving the second plate of the ferroelectric memory cell to ground, comparing the voltage on the first plate of the ferroelectric memory cell to a reference voltage at a sense node;

providing a first voltage to the sense node responsive to the voltage on the first plate of the ferroelectric memory cell being less than the reference voltage; and

providing a second voltage to the sense node responsive to the voltage on the first plate of the ferroelectric memory cell being greater than the reference voltage.

23. The method of claim 22, further comprising:

providing the second voltage to a complementary sense node responsive to the voltage on the first plate of the ferroelectric memory cell being less than the reference voltage; and

providing the first voltage to the complementary sense node responsive to the voltage on the first plate of the ferroelectric memory cell being greater than the reference voltage.

24. The method of claim 22, further comprising:

providing the first voltage to the second plate of the ferroelectric memory cell responsive to the voltage on the first plate of the ferroelectric memory cell being less than the reference voltage; and

providing the second voltage to the second plate of the ferroelectric memory cell responsive to the voltage on the first plate of the ferroelectric memory cell being greater than the reference voltage.

25. The method of claim 22, further comprising providing a reference signal to the sense node, the reference signal having the reference voltage.

26. The method of claim 22 wherein the reference voltage at the sense node is based on the voltage on the second plate of the ferroelectric memory cell resulting from providing the read voltage to the first plate of the ferroelectric memory cell.

27. The method of claim 22 wherein the reference voltage at the sense node is a first reference voltage responsive to a first polarization of the ferroelectric;

memory cell and the reference voltage at the sense node is a second reference voltage responsive to a second polarization of the ferroelectric memory cell.

28. An apparatus, comprising:

a first digit line;

a second digit line;

a ferroelectric memory cell including a ferroelectric capacitor, a first selection component, and a second selection component, the first selection component coupled between the first digit line and a first plate of the ferroelectric capacitor and the second selection component coupled between the second digit line and a second plate of the ferroelectric capacitor;

a first word line coupled to a gate of the first selection component;

a second word line coupled to a gate of the second selection component;

a sense component including a first sense node coupled to the first digit line through a switch and further including a second sense node coupled to the second digit line through an isolation switch, the sense component configured to latch voltages of the first and second sense nodes;

a first driver circuit coupled to the first digit line and configured to provide a read voltage when activated; and

a second driver circuit coupled to the second digit line and configured to provide a ground voltage when activated.

29. The apparatus of claim 28, further comprising a reference switch coupled to the second sense node and configured to provide a constant reference voltage to the first sense node when activated.

30. The apparatus of claim 28, further comprising a memory controller configured to control the first driver circuit to drive the first digit line to a read voltage and to deactivate the second selection component, the memory controller further configured to control the second driver circuit to drive the second digit line to ground and control the sense component to compare the voltage of the first sense node to the voltage of the second sense node.