FETs and Methods for Forming the Same
First Claim
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1. A method of forming a semiconductor device, the method comprising:
- forming a first epitaxial structure over a substrate in an NMOS region;
forming a second epitaxial structure over the substrate in a PMOS region;
forming a shallow trench isolation (STI) region between the first epitaxial structure and the second epitaxial structure;
patterning the first epitaxial structure and the second epitaxial structure to form a first plurality of vertical channel structures and a second plurality of vertical channel structures, respectively;
reshaping the first plurality of vertical channel structures and the second plurality of vertical channel structures, wherein after the reshaping, sidewalls of the first plurality of vertical channel structures and sidewalls the second plurality of vertical channel structures have lattice shifts;
forming a gate dielectric layer in first openings between the first plurality of vertical channel structures and in second openings between the second plurality of vertical channel structures;
filling the first openings and the second openings with a conductive material; and
growing a first epitaxial source/drain material over the first plurality of vertical channel structures and a second epitaxial source/drain material over the second plurality of vertical channel structures.
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Abstract
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
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Citations
20 Claims
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1. A method of forming a semiconductor device, the method comprising:
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forming a first epitaxial structure over a substrate in an NMOS region; forming a second epitaxial structure over the substrate in a PMOS region; forming a shallow trench isolation (STI) region between the first epitaxial structure and the second epitaxial structure; patterning the first epitaxial structure and the second epitaxial structure to form a first plurality of vertical channel structures and a second plurality of vertical channel structures, respectively; reshaping the first plurality of vertical channel structures and the second plurality of vertical channel structures, wherein after the reshaping, sidewalls of the first plurality of vertical channel structures and sidewalls the second plurality of vertical channel structures have lattice shifts; forming a gate dielectric layer in first openings between the first plurality of vertical channel structures and in second openings between the second plurality of vertical channel structures; filling the first openings and the second openings with a conductive material; and growing a first epitaxial source/drain material over the first plurality of vertical channel structures and a second epitaxial source/drain material over the second plurality of vertical channel structures. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming a semiconductor device, the method comprising:
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forming an epitaxial structure over a substrate, wherein forming the epitaxial structure comprises forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer successively over the substrate; patterning the epitaxial structure to form openings in the epitaxial structure, wherein the openings extend through the third epitaxial layer, through the second epitaxial layer, and into the first epitaxial layer, wherein after the patterning, remaining portions of the third epitaxial layer and remaining portions of the second epitaxial layer form a plurality of vertical channel structures, and remaining portions of the first epitaxial layer form a first source/drain region; reshaping the plurality of vertical channel structures, wherein after the reshaping, sidewalls of each of the plurality of the vertical channel structures comprise at least one lattice shift inward or outward relative to a center of a respective vertical channel structure; forming a metal gate in the openings; and forming an epitaxial material over the plurality of vertical channel structures to form a second source/drain region. - View Dependent Claims (14, 15, 16)
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17. A semiconductor device comprising:
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a fin protruding above a substrate; isolation regions on opposing sides of the fin; a gate dielectric material over an upper surface and over sidewalls of an upper portion of the fin, the upper portion of the fin protruding above an upper surface of the isolation regions; a quantum well between the gate dielectric material and the upper portion of the fin, the quantum well comprising one or more epitaxial materials; and a gate electrode over the gate dielectric material. - View Dependent Claims (18, 19, 20)
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Specification