NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20180068732A1
• Filed: 11/13/2017
• Published: 03/08/2018
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: MAEDA, Takashi
• Granted Patent: US 9,953,713 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. (canceled)

2. A memory device, comprising:

a first memory string including

a first selection transistor,

a first memory cell,

a second memory cell, and

a second selection transistor;

a second memory string including

a third selection transistor,

a third memory cell,

a fourth memory cell, and

a fourth selection transistor;

a bit line connected to the first selection transistor of the first memory string and the third selection transistor of the second memory string;

a source line connected to the second selection transistor of the first memory string and the fourth selection transistor of the second memory string;

a first word line connected to a gate of the first memory cell and a gate of the third memory cell;

a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell;

a first select gate line connected to a gate of the first selection transistor;

a second select gate line connected to a gate of the third selection transistor; and

a control circuit configured to perform

a first erasing operation of erasing data stored in the first memory cell and data stored in the second memory cell without erasing data stored in the third memory cell and data store in the fourth memory cell.

3. The memory device according to claim 2, wherein

the control circuit performs the first erasing operation by

applying a first voltage to the bit line,

applying a second voltage to the first select gate line,

applying a third voltage to the second select gate line,

applying a fourth voltage to the first word line, and

applying a fifth voltage to the second word line.

4. The memory device according to claim 3, wherein

the second voltage is lower than the first voltage,

the third voltage is substantially same with the first voltage,

the fourth voltage is lower than the second voltage, and

the fifth voltage is substantially same with the fourth voltage.

5. The memory device according to claim 3, wherein

the second voltage is set with respect to the first voltage so as to cause a Gate Induced Drain Leakage current in the first selection transistor, and

the third voltage is set with respect to the first voltage so as to avoid the Gate Induced Drain Leakage current in the third selection transistor.

6. The memory device according to claim 2, wherein

the control circuit is further configure to perform

a second erasing operation of erasing the data stored in the third memory cell and the data stored in the fourth memory cell without erasing the data stored in the first memory cell and the data store in the second memory cell.

7. The memory device according to claim 2, further comprising:

a third select gate line connected to a gate of the second selection transistor; and

a fourth select gate line connected to a gate of the fourth selection transistor.

8. The memory device according to claim 2, wherein

in the first memory string,

the first selection transistor is provided in plurality, and

the second selection transistor is provided in plurality, and

in the second memory string,

the third selection transistor is provided in plurality, and

the fourth selection transistor is provided in plurality.

9. The memory device according to claim 2, wherein

the first memory string further includes

a first dummy transistor between the first selection transistor and the first memory cell, and

a second dummy transistor between the second memory cell and the second selection transistor, and

the second memory string further includes

a third dummy transistor between the third selection transistor and the third memory cell, and

a fourth dummy transistor between the fourth memory cell and the fourth selection transistor.

10. The memory device according to claim 2, wherein

in the first memory string,

the first selection transistor and the first memory cell are vertically arranged, and

the second memory cell and the second selection transistor are vertically arranged, and

in the second memory string,

the third selection transistor and the third memory cell are vertically arranged, and

the fourth memory cell and the fourth selection transistor are vertically arranged.

11. The memory device according to claim 2, wherein

the first memory string further includes

a first control transistor between the first memory cell and the second memory cell, and

the second memory string further includes

a second control transistor between the third memory cell and the fourth memory cell.