High Speed and High Voltage Driver

• US 20180076812A1
• Filed: 09/11/2017
• Published: 03/15/2018
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Wu, Gary Chunshien
• Granted Patent: US 9,979,387 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Claims

1. (canceled)

2. A high speed high voltage (HSHV) open drain driver comprising:

a main stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver;

a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of transistors of a second type;

wherein;

gate nodes of a first to a last transistor of the main stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the biasing stack,

source nodes of transistors of the main stack of transistors are coupled in a one to one relationship to gate nodes of transistors of the biasing stack,

the output node is a drain node of an output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and

transistors of the main stack and the biasing stack having desired operating voltages substantially smaller than the high voltage.

3. The HSHV open drain driver of claim 2, wherein the HSHV open drain driver operates in:

an ON mode, wherein a voltage at the output node is substantially equal to the reference voltage, and

an OFF mode, wherein the voltage at the output node is substantially equal to the high voltage,

wherein operation in one of the ON mode and the OFF mode is based on a voltage level of the input signal to the HSHV driver.

4. The HSHV open drain driver of claim 2, wherein the main stack comprises a number of stacked transistors equal to or higher than three.

5. The HSHV open drain driver of claim 2, wherein the first type is N-type and the second type is P-type.

6. The HSHV open drain driver of claim 3, wherein in the ON mode, all transistors of the main stack and the biasing stack are ON, and in the OFF mode, all transistors of the main stack and the biasing stack are OFF.

7. The HSHV open drain driver of claim 2, wherein:

transistors of the main stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor,

the last transistor of the main stack is the output transistor and the first transistor of the main stack is an input transistor of the HSHV open drain driver,

a gate node of the input transistor is configured to receive the input signal,

a source node of the input transistor is coupled to the reference voltage, and

common source-drain nodes of the first to the last transistor of the main stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack.

8. The HSHV open drain driver of claim 7, wherein the input signal is configured to switch between the reference voltage and a voltage higher than the reference voltage and lower than each of the desired operating voltages.

9. The HSHV open drain driver of claim 7, wherein the biasing voltages to the main stack are provided by coupling of the biasing circuit to the gate nodes and common source-drain nodes of the main stack.

10. The HSHV open drain driver of claim 7, wherein:

the biasing circuit further comprises a plurality of series connected resistors configured as a resistive voltage divider between the source node of the first transistor of the main stack and the drain node of the last transistor of the main stack, and

resistive nodes of the resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the gate nodes of the transistors of the main stack in a one to one relationship.

11. The HSHV open drain driver of claim 10, wherein the coupling from the resistive nodes of the resistive voltage dividers to the gate nodes is one or more of a) a direct coupling, b) a resistive coupling, and c) a transistor coupling.

12. The HSHV open drain driver of claim 11, wherein the coupling through a transistor comprises a source-follower circuit.

13. The HSHV open drain driver of claim 10, wherein the biasing circuit further comprises a plurality of capacitors each connected between a resistive node of the resistive voltage divider and the source node of the first transistor of the main stack.

14. The HSHV open drain driver of claim 10, wherein:

the biasing circuit further comprises a plurality of series connected capacitors configured as a capacitive voltage divider between the source node of the first transistor of the main stack and the output node coupled to the drain of the last transistor of the main stack, and

capacitive nodes of the capacitive voltage divider connecting two consecutive capacitors of the plurality of series connected capacitors are coupled to the gate nodes of the transistors of the main stack in a one to one relationship.

15. The HSHV open drain driver of claim 14, further comprising coupling between the plurality of series connected capacitors from the biasing circuit and the gate nodes of the transistors of the main stack.

16. The HSHV open drain driver of claim 15, wherein the coupling between the plurality of series connected capacitors from the biasing circuit and the gate nodes of the transistors of the main stack is through a transistor.

17. The HSHV open drain driver of claim 7, wherein the biasing circuit is configured to provide the biasing voltages of the HSHV open drain driver at an output switching frequency of 0 Hz to 20 MHz.

18. The HSHV open drain driver of claim 7, wherein the biasing circuit is configured to provide the biasing voltages of the HSHV open drain driver at an output switching frequency of 0 Hz to 100 MHz.

19. The HSHV open drain driver of claim 7, wherein the biasing circuit is configured to provide the biasing voltages of the HSHV open drain driver at an output switching frequency above 100 MHz.

20. The HSHV open drain driver of claim 17, wherein biasing of the transistors of the main stack does not exceed the desired operating voltages across any two terminals of the transistors.

21. The HSHV open drain driver of claim 18, wherein biasing of the transistors of the main stack does not exceed the desired operating voltages across any two terminals of the transistors.

22. The HSHV open drain driver of claim 19, wherein biasing of the transistors of the main stack does not exceed the desired operating voltages across any two terminals of the transistors.