PACKAGE STRUCTURE WITH BUMP
First Claim
1. A package structure, comprising:
- a molding compound;
an integrated circuit chip in the molding compound, wherein the integrated circuit chip has a chip edge;
a passivation layer below the integrated circuit chip and the molding compound;
a redistribution layer in the passivation layer; and
first bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the first bumps are inside the chip edge and arranged along the chip edge; and
second bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the second bumps are outside the chip edge and arranged along the chip edge, and wherein the first bumps are next to the second bumps, and the first and second bumps are spaced apart from the chip edge.
1 Assignment
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Accused Products
Abstract
A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.
20 Citations
20 Claims
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1. A package structure, comprising:
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a molding compound; an integrated circuit chip in the molding compound, wherein the integrated circuit chip has a chip edge; a passivation layer below the integrated circuit chip and the molding compound; a redistribution layer in the passivation layer; and first bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the first bumps are inside the chip edge and arranged along the chip edge; and second bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the second bumps are outside the chip edge and arranged along the chip edge, and wherein the first bumps are next to the second bumps, and the first and second bumps are spaced apart from the chip edge. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A package structure, comprising:
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a package layer; an integrated circuit chip in the package layer, wherein the integrated circuit chip has a chip edge; a passivation layer below the integrated circuit chip and the package layer, wherein the passivation layer comprises a first region and a second region adjoining the first region, and there is a boundary between the first and second regions, and wherein the boundary is substantially aligned to the chip edge; a redistribution layer in the passivation layer, wherein the redistribution layer extends across the boundary; first bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the first bumps are in the first region; and second bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the second bumps are in the second region, and wherein the first bumps and the second bumps are next to the boundary and arranged along the boundary without overlapping the boundary. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A package structure, comprising:
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a package layer; a first chip in the package layer, wherein the first chip has a first chip edge; a second chip in the package layer, wherein the second chip has a second chip edge that is next to the first chip edge, and there is an interval between the first and second chip edges; a passivation layer below the first chip, the second chip and the package layer; redistribution lines in the passivation layer; and bumps electrically connected to the first chip and the second chip through the redistribution lines, wherein the bumps comprise; first bumps inside the first chip edge; second bumps inside the second chip edge; and third bumps outside the first and second chip edges, wherein there is a bump pitch between one of the first bumps and one of the third bumps that are next to each other, wherein the third bumps are arranged outside a region between the first and second chip edges to partially surround the first and second chip edges if the interval is less than the bump pitch, and one or more of the third bumps are arranged within the region if the interval is not less than the bump pitch. - View Dependent Claims (17, 18, 19, 20)
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Specification