PROCESSOR AND METHOD FOR EXECUTING MATRIX MULTIPLICATION OPERATION ON PROCESSOR
First Claim
1. A processor comprising:
- a data bus; and
an array processor having k processing units;
the data bus configured to sequentially read n columns of row vectors from an M×
N multiplicand matrix and input the n columns of row vectors to each processing unit in the array processor, read an n×
k submatrix from an N×
K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation; and
the each processing unit in the array processor configured to execute in parallel a vector multiplication operation on the input row and column vectors, and the each processing unit comprising a Wallace tree multiplier having n multipliers and n-1 adders,wherein n, k, M, and N are integers greater than 1.
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Accused Products
Abstract
A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an array processor having k processing units. The data bus is configured to sequentially read n columns of row vectors from an M×N multiplicand matrix and input same to each processing unit in the array processor, read an n×k submatrix from an N×K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation. Each processing unit in the array processor is configured to execute in parallel a vector multiplication operation on the input row and column vectors. Each processing unit includes a Wallace tree multiplier having n multipliers and n-1 adders. This implementation improves the processing efficiency of a matrix multiplication operation.
27 Citations
12 Claims
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1. A processor comprising:
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a data bus; and an array processor having k processing units; the data bus configured to sequentially read n columns of row vectors from an M×
N multiplicand matrix and input the n columns of row vectors to each processing unit in the array processor, read an n×
k submatrix from an N×
K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation; andthe each processing unit in the array processor configured to execute in parallel a vector multiplication operation on the input row and column vectors, and the each processing unit comprising a Wallace tree multiplier having n multipliers and n-1 adders, wherein n, k, M, and N are integers greater than 1. - View Dependent Claims (2, 3, 4, 5, 11)
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6. A method for executing a matrix multiplication operation on a processor, the processor comprising an array processor having k processing units, the method comprising:
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reading n columns of row vectors in an M×
N multiplicand matrix to each processing unit in the array processor, the each processing unit comprising a Wallace tree multiplier having n multipliers and n-1 adders;reading each of n rows of column vectors in an n×
k submatrix in an N×
K multiplier matrix to a corresponding processing unit in the array processor respectively;executing in parallel a vector multiplication operation on each column vector and the row vector by using the processing units, the Wallace tree multiplier in the each processing unit being configured to execute in parallel a multiplication operation and an addition operation in the vector multiplication operation; and outputting a result obtained by the each processing unit after executing the multiplication operation, wherein n, k, M, and N are integers greater than 1. - View Dependent Claims (7, 8, 9, 10, 12)
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Specification