METHOD AND SYSTEM FOR VERTICAL INTEGRATION OF ELEMENTAL AND COMPOUND SEMICONDUCTORS

• US 20180114726A1
• Filed: 10/19/2017
• Published: 04/26/2018
• Est. Priority Date: 10/21/2016
• Status: Active Grant

• Current Assignee: Qromis, Inc.
• Original Assignee: Qromis, Inc.
• Inventors: Odnoblyudov, Vladimir, Basceri, Cem, Farrens, Shari
• Granted Patent: US 10,074,567 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/0605 : integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0617 : comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Abstract

A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, forming a GaN layer coupled to the second silicon layer, forming a GaN based device coupled to the GaN layer, removing the engineered substrate to expose a back surface of the first silicon layer, forming a silicon based device coupled to the back surface of the first silicon layer, forming a via from the back surface of the first silicon layer, filling the via with a conducting material, and interconnecting the GaN based device and the silicon based device through the via.

Claims

1. A method of fabricating a semiconductor structure, the method comprising:

providing an engineered substrate, the engineered substrate comprising;

a polycrystalline substrate;

a barrier layer encapsulating the polycrystalline substrate; and

a bonding layer coupled to the barrier layer;

forming a first silicon layer coupled to the bonding layer, the first silicon layer being substantially single crystalline and having a surface in a first crystalline orientation;

forming a dielectric layer coupled to the first silicon layer;

forming a second silicon layer coupled to the dielectric layer, the second silicon layer being substantially single crystalline and having a surface in a second crystalline orientation different from the first crystalline orientation;

forming a gallium nitride (GaN) layer coupled to the second silicon layer by epitaxial growth;

forming a gallium nitride (GaN) based device coupled to the GaN layer by epitaxial growth;

removing the engineered substrate to expose a back surface of the first silicon layer;

forming a silicon based device coupled to the back surface of the first silicon layer;

forming a via from the back surface of the first silicon layer, the via through the first silicon layer, the dielectric layer, the second silicon layer, and the GaN layer;

filling the via with a conducting material; and

interconnecting the GaN based device and the silicon based device through the via.

2. The method of claim 1 wherein the polycrystalline substrate comprises polycrystalline aluminum gallium nitride (AlGaN).

3. The method of claim 1 wherein the barrier layer comprises silicon nitride.

4. The method of claim 1 wherein the first crystalline orientation is (100) orientation of silicon, and the second crystalline orientation is (111) orientation of silicon.

5. The method of claim 1 wherein the silicon based device comprises a complementary metal-oxide-semiconductor (CMOS) device.

6. The method of claim 1 further comprising, before forming the GaN layer, forming a buffer layer coupled to the second silicon layer by epitaxial growth, and wherein the GaN layer is formed on the buffer layer.

7. A method of fabricating a semiconductor structure, the method comprising:

providing an engineered substrate, the engineered substrate comprising;

a polycrystalline substrate;

a barrier layer encapsulating the polycrystalline substrate; and

a bonding layer coupled to the barrier layer;

forming a first silicon layer coupled to the bonding layer, the first silicon layer being substantially single crystalline and having a surface in a first crystalline orientation;

forming a first dielectric layer coupled to the first silicon layer;

forming a second silicon layer coupled to the first dielectric layer, the second silicon layer being substantially single crystalline and having a surface in a second crystalline orientation different from the first crystalline orientation;

forming a gallium nitride (GaN) layer coupled to the second silicon layer by epitaxial growth;

removing the engineered substrate to expose a back surface of the first silicon layer;

forming a first plurality of vias from the back surface of the first silicon layer, each of the first plurality of vias through the first silicon layer, the first dielectric layer, the second silicon layer, and into the GaN layer;

filling each of the first plurality of vias with a first conductive material;

forming a second dielectric layer coupled to the first silicon layer;

forming a third silicon layer coupled to the second dielectric layer, the third silicon layer being substantially single crystalline and having a surface in the first crystalline orientation;

forming a second via from a surface of the third silicon layer, the second via through the third silicon layer and the second dielectric layer to connect with one of the first plurality of vias;

filling the second via with a second conductive material;

forming a silicon based device coupled to the third silicon layer and the second via;

forming a third via from a surface of the GaN layer, the third via connecting with the second via through the one of the first plurality of vias;

filling the third via with a third conductive material; and

forming a gallium nitride (GaN) based device coupled to the GaN layer and the third via, wherein the GaN based device is coupled to the silicon based device through the third via, the one of the first plurality of vias, and the third via.

8. The method of claim 7 wherein the polycrystalline substrate comprises polycrystalline aluminum gallium nitride (AlGaN).

9. The method of claim 7 wherein the barrier layer comprises silicon nitride.

10. The method of claim 7 wherein the first crystalline orientation is (100) orientation of silicon, and the second crystalline orientation is (111) orientation of silicon.

11. The method of claim 7 wherein the silicon based device comprises a complementary metal-oxide-semiconductor (CMOS) device.

12. The method of claim 7 further comprising, before forming the GaN layer, forming a buffer layer coupled to the second silicon layer by epitaxial growth, and wherein the GaN layer is formed on the buffer layer.

13. A method of fabricating a semiconductor structure, the method comprising:

providing an engineered substrate, the engineered substrate comprising;

a polycrystalline substrate;

a barrier layer encapsulating the polycrystalline substrate; and

a bonding layer coupled to the barrier layer;

forming a first silicon layer coupled to the bonding layer, the first silicon layer being substantially single crystalline and having a surface in a first crystalline orientation;

forming a first dielectric layer coupled to the first silicon layer;

forming a second silicon layer coupled to the first dielectric layer, the second silicon layer being substantially single crystalline and having a surface in a second crystalline orientation different from the first crystalline orientation;

forming a gallium nitride (GaN) layer coupled to the second silicon layer by epitaxial growth;

removing the engineered substrate to expose a back surface of the first silicon layer;

forming a first plurality of vias from the back surface of the first silicon layer, each of the first plurality of vias through the first silicon layer, the first dielectric layer, the second silicon layer, and into the GaN layer;

filling each of the first plurality of vias with a first conductive material;

forming a second dielectric layer coupled to the first silicon layer;

forming a third silicon layer coupled to the second dielectric layer, the third silicon layer being substantially single crystalline and having a surface in the first crystalline orientation;

forming a second via from a surface of the GaN layer, the second via connecting with one of the first plurality of vias;

filling the second via with a second conductive material;

forming a gallium nitride (GaN) based device coupled to the GaN layer and the second via;

forming a third via from a surface of the third silicon layer, the third via through the third silicon layer and the second dielectric layer to connect with the one of the first plurality of vias, thereby connecting with the second via;

filling the third via with a third conductive material; and

forming a silicon-based coupled to the third silicon layer and the third via, wherein the silicon based device is coupled to the GaN based device through the third via, the one of the first plurality of vias, and the second via.

14. The method of claim 13 wherein the polycrystalline substrate comprises polycrystalline aluminum gallium nitride (AlGaN).

15. The method of claim 13 wherein the barrier layer comprises silicon nitride.

16. The method of claim 13 wherein the first crystalline orientation is (100) orientation of silicon, and the second crystalline orientation is (111) orientation of silicon.

17. The method of claim 13 wherein the silicon based device comprises a complementary metal-oxide-semiconductor (CMOS) device.

18. The method of claim 13 further comprising, before forming the GaN layer, forming a buffer layer coupled to the second silicon layer by epitaxial growth, and wherein the GaN layer is formed on the buffer layer.

19. The method of claim 13 wherein the second via is formed before the GaN based device is formed.

20. The method of claim 13 wherein the second via is formed after the GaN based device is formed.