MULTI-STAGE TEST RESPONSE COMPACTORS

• US 20180156867A1
• Filed: 10/02/2017
• Published: 06/07/2018
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Janusz, Tyszer, Jerzy, Mrugalski, Grzegorz, Kassab, Mark, Cheng, Wu-Tung
• Granted Patent: US 10,120,024 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Claims

1. An apparatus for compacting test responses of a circuit-under-test, the apparatus comprising:

a first compactor comprising a plurality of first-compactor inputs and a first-compactor output;

a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; and

a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor.

2. The apparatus of claim 1, wherein the second spatial compactor is feedback free.

3. The apparatus of claim 1, wherein the second spatial compactor comprises a network of XOR or XNOR gates.

4. The apparatus of claim 1, wherein the second spatial compactor is a pipelined spatial compactor.

6. The apparatus of claim 1, wherein the register comprises two or more sequential elements coupled in series.

7. The apparatus of claim 1, wherein the register is operable to serially load the test response bits.

8. The apparatus of claim 1, wherein the first compactor comprises a plurality of first-compactor outputs.

9. The apparatus of claim 1, wherein the second compactor comprises a plurality of second-compactor outputs.

10. The apparatus of claim 1, further comprising:

a first set of masking logic coupled to the plurality of first-compactor inputs; and

a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs.

11. The apparatus of claim 10, further comprising selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs.

12. The apparatus of claim 11, wherein the selection logic comprises a network of logic gates configured according to polynomials.

13. The apparatus of claim 12, wherein at least some of the logic gates are XOR or XNOR gates.

14. The apparatus of claim 12, wherein the polynomials describe respective relationships between at least one selection logic input and at least one selection logic output.

15. The apparatus of claim 11, wherein the register is a first register, wherein the selection logic comprises a plurality of selection-logic inputs, and wherein the apparatus further comprises a second register having a second-register input and a plurality of second-register outputs, the plurality of second-register outputs being coupled to the plurality of selection-logic inputs.

16. The apparatus of claim 11, wherein the masking instruction bits are uncompressed bits received from an external tester, an on-chip memory, or an on-chip decompressor.

17. One or more computer-readable media storing circuit design information for implementing the apparatus of claim 1.

18. One or more computer-readable media storing computer-executable instructions for causing a computer to create the apparatus of claim 1.

5. (canceled)

19. -38. (canceled)