Methods and Devices to Improve Switching Time by Bypassing Gate Resistor

• US 20180167062A1
• Filed: 12/12/2016
• Published: 06/14/2018
• Est. Priority Date: 12/12/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Shanjani, Payman, Shapiro, Eric S.
• Granted Patent: US 10,396,772 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Claims

1. A switching circuit comprising:

a first node;

a second node;

a main FET switch;

a gate resistor;

a bypass switch, and

wherein;

a drain of the main FET switch is connected to the first node and a source of the main FET switch is coupled to the second node;

the bypass switch is coupled across the gate resistor; and

the gate resistor couples a control voltage to a gate of the main switch.

2. The switching circuit of claim 1, wherein:

the control voltage is configured to transition the main switch from an OFF to an ON state and vice versa; and

the bypass switch is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main switch is transitioning from the OFF to the ON state and vice versa, thereby bypassing the gate resistor.

3. The switching circuit of claim 2, wherein the bypass switch comprises a first bypass switch and a second bypass switch;

the first and the second bypass switches being configured in parallel and wherein;

the first bypass switch is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main switch is transitioning from the OFF to the ON state, thereby bypassing the gate resistor, and

the second bypass switch is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main switch is transitioning from the ON to the OFF state, thereby by passing the gate resistor.

4. The switching circuit of claim 3, wherein the first bypass switch comprises an n-channel FET and the second bypass switch comprises a p-channel FET;

wherein;

drains of the n-channel and the p-channel FETs are connected together;

sources of the n-channel and the p-channel FETs are connected together;

drains of the n-channel and the p-channel FETs are connected to gates of the n-channel and the p-channel FETs respectively, and

the gate resistor is coupled across the drains and sources of the n-channel and the p-channel FETs.

5. The switching circuit of claim 4, wherein the n-channel FET and the p-channel FET are NMOS FET and PMOS FET respectively.

6. A switching circuit comprising:

a first node;

a second node;

a main FET switch;

a series configuration of a first gate resistor and a second gate resistor;

a bypass n-channel FET switch;

a bypass p-channel FET switch;

wherein;

a drain of the main FET switch is connected to the first node and a source of the main FET switch is coupled to the second node;

a control voltage is coupled through the first and the second gate resistors to a gate of the main switch;

drains of the n-channel and the p-channel FETs are connected together;

sources of the n-channel and the p-channel FETs are connected together;

drains of the n-channel and the p-channel FETs are connected to gates of the n-channel and the p-channel FETs respectively, and

the first gate resistor is coupled across the drains and sources of the n-channel and the p-channel FETs;

wherein;

the control voltage is configured to transition the main switch from an OFF to an ON state and vice versa;

the n-channel FET is configured to be open when the main FET switch is in the OFF or the ON state and to be closed when the main FET switch is transitioning from the OFF to the ON state, thereby bypassing the first gate resistor, and

the p-channel FET is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main FET switch is transitioning from the ON to the OFF state, thereby by passing the first gate resistor.

7. A switching circuit comprising:

a first node;

a second node;

a first terminal;

a second terminal;

a main FET switch stack;

a bypass FET switch stack, and

wherein;

the main FET switch stack comprises;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and

a plurality of main gate resistors, the plurality of the main gate resistors connecting the second terminal to corresponding gates of the plurality of the main FET switches;

the bypass FET switch stack comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors;

the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the first terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the first terminal, and

a through resistor;

the through resistor connecting the first terminal to the second terminal;

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the first terminal and farthest from the second terminal are connected to the first terminal;

the sources of the bypass FET switches closest to the second terminal and farthest from the first terminal are connected to the second terminal;

wherein;

a supply voltage applied to the first terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa;

the plurality of the first bypass FET switches are configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main FET switch is transitioning from the OFF to the ON state, and

the second bypass switch is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main switch is transitioning from the ON to the OFF state.

10. The switching circuit of claim 7, further comprising a plurality of drain-source resistances, the plurality of the drain-source resistors being coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches.

8. A switching circuit comprising:

a first node;

a second node;

a first terminal;

a second terminal;

a main FET switch stack; and

a bypass FET switch stack, and

wherein;

the main FET switch stack comprises;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and

a plurality of main gate resistors, the plurality of the main gate resistors connecting the second terminal to corresponding gates of the plurality of the main FET switches;

the bypass FET switch stack comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors;

the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the first terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the first terminal, and

a plurality of drain-source resistances, the plurality of the drain-source resistors being coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches;

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the first terminal and farthest from the second terminal are connected to the first terminal;

the sources of the bypass FET switches closest to the second terminal and farthest from the first terminal are connected to the second terminal;

wherein;

a supply voltage applied to the first terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa;

the plurality of the first bypass FET switches are configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main FET switch is transitioning from the OFF to the ON state, and

the second bypass switch is configured to be open when the main switch is in the OFF or the ON state and to be closed when the main switch is transitioning from the ON to the OFF state.

9. The switching circuit of claim 8, wherein the ratio of a size of the bypass FET switch to a size of the main FET switch is less than 1/100.

11. The switching circuit of claim 8, wherein the plurality of the first bypass and the second bypass FET switches are NMOS and PMOS switches respectively.

12. A switching circuit comprising:

a first node;

a second node;

a main FET switch stack;

a bypass switching block;

an input terminal, and

wherein;

the main FET switch stack comprises;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, wherein gates of the plurality of the main FET switches are connected together;

the bypass switching block comprises a common switch coupled across a common gate resistor;

the common gate resistor connects the input terminal to the gates of the plurality of the main FET switches, and

wherein;

the control voltage is applied to the input terminal and is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa, and

the common switch is configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main FET switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the common gate resistor.

14. The switching circuit of claim 12, wherein the common switch comprises an n-channel FET and a p-channel FET,

wherein:

drains of the n-channel and the p-channel FETs are connected together;

sources of the n-channel and the p-channel FETs are connected together;

drains of the n-channel and the p-channel FETs are connected to gates of the n-channel and the p-channel FETs respectively, and

the gate resistor is coupled across the drains and sources of the n-channel and the p-channel FETs.

15. The switching circuit of claim 14, wherein the n-channel FET and the p-channel FET are NMOS FET and PMOS FET respectively.

18. The switching circuit of claim 12, wherein:

the common gate resistor comprises a series arrangement of a plurality of drain-source resistors;

the common switch comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors, the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the input terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the input terminal,

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the input terminal and farthest from the gates of the plurality of the main FET switches are connected to the input terminal;

the sources of the bypass FET switches closest to the gates of the plurality of the main FET switches and farthest from the first terminal are connected to the gates of the plurality of the main FET switches;

the gates and the drains of the plurality of the first bypass FET switches are connected together;

the gates and the drains of the plurality of the second bypass FET switches are connected together, and

the plurality of drain-source resistors are coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches.

13. A switching circuit comprising:

a first node;

a second node;

an input terminal;

a main switch stack;

the main switch stack comprising;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and

a plurality of main bypass switch blocks, and

wherein;

each of the plurality of the main bypass switch blocks comprises a bypass switch, the bypass switch coupling across a main gate resistor, the main gate resistors connecting at one end together and to the input terminal and at another end to corresponding gates of the plurality of the main FET switches, and

wherein;

a control voltage applied to the input terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa, and

the bypass switches are configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the main gate resistors.

16. The switching circuit of claim 13, wherein each of the bypass switches comprises an n-channel FET and a p-channel FET,

wherein:

drains of the n-channel and the p-channel FETs are connected together;

sources of the n-channel and the p-channel FETs are connected together;

drains of the n-channel and the p-channel FETs are connected to gates of the n-channel and the p-channel FETs respectively, and

the gate resistor is coupled across the drains and sources of the n-channel and the p-channel FETs.

17. The switching circuit of claim 16, wherein the n-channel FET and the p-channel FET are NMOS FET and PMOS FET respectively.

19. The switching circuit of claim 13, wherein:

each of the main gate resistors comprises a series arrangement of a plurality of drain-source resistors;

each of the main bypass switches comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors, the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the input terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the first terminal,

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the first terminal and farthest from the corresponding gates of the plurality of the main switches are connected to the first terminal;

the sources of the bypass FET switches closest to the corresponding gates of the plurality of the main switches and farthest from the first terminal are connected to the gates of the plurality of the main FET switches;

the gates and the drains of the plurality of the first bypass FET switches are connected together;

the gates and the drains of the plurality of the second bypass FET switches are connected together, and

the plurality of drain-source resistors are coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches.

20. A switching circuit comprising:

a first node;

a second node;

an input terminal;

an output terminal;

a main switch stack, the main switch stack comprising;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node;

series arrangements of a plurality of main bypass switch blocks and a plurality of corresponding main series resistors;

a bypass switch block, and

a common series resistor;

wherein;

the plurality of the main bypass switch blocks comprises a plurality of corresponding bypass switches and a plurality of corresponding main gate resistors, the plurality of the main bypass switches being coupled across the corresponding plurality of the main gate resistors;

the series arrangements of the plurality of the main bypass switch blocks and the plurality of the corresponding main resistors couple the output terminal to corresponding gates of the plurality of the main FET switches;

the bypass switch block comprises a common switch coupled across a gate series resistor, and

the input terminal is connected to the output terminal via a series arrangement of the bypass switch block with the common series resistor;

wherein;

a control voltage applied to the input terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa, and

the plurality of the bypass switches and the common switch are configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the plurality of the main gate resistors and the gate series resistors respectively.

21. The switching circuit of claim 20, wherein each of the common switch and the plurality of the bypass switches comprises an n-channel FET and a p-channel FET, wherein:

drains of the n-channel and the p-channel FETs are connected together;

sources of the n-channel and the p-channel FETs are connected together;

drains of the n-channel and the p-channel FETs are connected to gates of the n-channel and the p-channel FETs respectively, and

the gate series resistor and the plurality of the main gate resistors are coupled across the drains and sources of the corresponding n-channel and p-channel FETs.

22. The switching circuit of claim 20, wherein:

i) each of the main gate resistors comprises a series arrangement of a plurality of main drain-source resistors;

ii) the common series resistor comprises a series arrangement of the plurality of common drain-source resistors;

iii) each of the main bypass switches comprises;

a series arrangement of a plurality of first main bypass FET switches;

a series arrangement of a plurality of second main bypass FET switches;

a plurality of first main bypass gate resistors, the plurality of the first main bypass gate resistors connecting corresponding gates of the plurality of the first main bypass FET switches to corresponding drains of the plurality of the first main bypass FET switches;

a plurality of second main bypass gate resistors;

the plurality of the second main bypass gate resistors connecting corresponding gates of the plurality of the second main bypass FET switches to corresponding drains of the plurality of the second main bypass FET switches;

iv) the bypass switch block comprises;

a series arrangement of a plurality of first common bypass FET switches;

a series arrangement of a plurality of second common bypass FET switches;

a plurality of first common bypass gate resistors, the plurality of the first common bypass gate resistors connecting corresponding gates of the plurality of the first common bypass FET switches to corresponding drains of the plurality of the first common bypass FET switches;

a plurality of second common bypass gate resistors;

the plurality of the second common bypass gate resistors connecting corresponding gates of the plurality of the second common bypass FET switches to corresponding drains of the plurality of the second common bypass FET switches;

and wherein;

drains and sources of the first main bypass FET switches are connected to corresponding drains and sources of the second main bypass FET switches respectively;

drains and sources of the first common bypass FET switches are connected to corresponding drains and sources of the second common bypass FET switches respectively;

the plurality of the main drain-source resistors are coupled across the corresponding drains and sources of the plurality of the first main and the second main bypass FET switches;

the plurality of the common drain-source resistors are coupled across the corresponding drains and sources of the plurality of the first common and the second common bypass FET switches;

each of the plurality of the main resistors have a main resistor first end and a main resistor second end;

the common series resistor has a common series resistor first end and a common series resistor second end;

the common series resistor second end is connected to the output terminal;

the main resistor first ends of the plurality of the main series resistors are all connected to the common resistor second end;

the drains of the first and the second main bypass FET switches closest to the corresponding main resistor second ends and farthest from the corresponding gates of the plurality of the main switches are connected to the corresponding main resistor second ends;

the sources of the first and the second main bypass FET switches farthest from the corresponding main resistor second ends and closest to the corresponding gates of the plurality of the main switches are connected to the corresponding gates of the plurality of the main switches;

the drains of the first and the second common bypass FET switches closest to the input terminal and farthest from the common series resistor first end are connected to the input terminal, and

the sources of the first and the second common bypass FET switches closest to the common series resistor first end farthest from the input terminal are connected to the common series resistor first end.

23. The switching circuit of claim 22, wherein proceeding from a first main bypass switch block closest to the first node and farthest from the second node to a last main bypass switch block closest to the second node and farthest from the first node, the main bypass switch blocks comprise a decreasing number of the first bypass FET switches and a decreasing number of the second bypass FET switches.

24. A switching method in an integrated circuit, the method comprising the steps of:

providing a first node;

providing a second node;

providing a main FET switch;

providing a gate resistor, and

providing a bypass switch;

connecting a drain of the main FETs to first node and coupling a source of the main FET switch to the second node;

coupling the bypass switch across the gate resistor;

coupling a control voltage to a gate of the main switch via the gate resistor;

transitioning the main switch from an OFF to an ON state and vice versa by the control voltage, and

opening the bypass switch when the main switch is in the OFF or the ON state and closing the bypass switch when the main switch is transitioning from the OFF state to the ON state and vice versa, thereby bypassing the gate resistance.

25. A switching method in an integrated circuit, the method comprising the steps of:

providing a first node;

providing a second node;

providing a main FET switch;

providing a series configuration of a first gate resistor and a second gate resistor;

providing a bypass n-channel FET switch;

providing a bypass p-channel FET switch;

connecting a drain of the main FET switch to the first node and coupling a source of the main FET switch to the second node;

coupling a control voltage through the first and the second gate resistors to a gate of the main switch;

connecting drains of the n-channel and the p-channel FETs together;

connecting sources of the n-channel and the p-channel FETs together;

connecting drains of the n-channel and the p-channel FETs to gates of the n-channel and the p-channel FETs respectively;

coupling the first gate resistor across the drains and sources of the n-channel and the p-channel FETs, and

transitioning the main switch from an OFF to an ON state and vice versa using the control voltage;

opening the n-channel FET switch when the main FET switch is in the OFF or the ON state and closing the n-channel FET when the main FET switch is transitioning from the OFF to the ON state, thereby bypassing the first gate resistor, and

opening the p-channel FET switch when the main switch is in the OFF or the ON state and closing the p-channel FET switch when the main FET switch is transitioning from the ON to the OFF state, thereby by passing the first gate resistor.

26. A switching method in an integrated circuit, the method comprising the steps of:

providing a first node;

providing a second node;

providing an input terminal;

providing an output terminal;

providing a main switch stack, the main switch stack comprising;

a series arrangement of a plurality of main FET switches;

series arrangements of a plurality of main bypass switch blocks and a plurality of corresponding main series resistors, the plurality of the main bypass switching blocks comprising a plurality of corresponding bypass switches and a plurality of corresponding main gate resistors;

coupling the plurality of the bypass switches across the corresponding plurality of the main gate resistors;

coupling the series arrangement of the plurality of main FET switches between the first node and the second node;

providing a bypass switch block, the bypass switch block comprising a common switch and a gate series resistor;

coupling the common switch across the gate series resistor;

providing a common series resistor;

coupling the output terminal to corresponding gates of the plurality of the main FET switches via the series arrangements of the plurality of the main bypass switch blocks and the plurality of the corresponding main resistors;

connecting the input terminal to the output terminal via series arrangement of the bypass switch block with the common series resistor, and

applying a control voltage to the input terminal thereby transitioning the plurality of the main FET switches from an OFF to an ON state and vice versa, and

opening the plurality of the bypass switches and the common switch when the plurality of the main FET switches are in the OFF or the ON state and closing the plurality of the bypass switches and the common switch when the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the plurality of the main gate resistors and the gate series resistors respectively.

27. A switching circuit comprising:

a first node;

a second node;

a first terminal;

a second terminal;

a third terminal;

a fourth terminal;

a main FET switch stack;

a bypass FET switch stack, and

wherein;

the main FET switch stack comprises;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and

a plurality of main gate resistors, the plurality of the main gate resistors connecting the second terminal to corresponding gates of the plurality of the main FET switches;

the bypass FET switch stack comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors;

the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the third terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the fourth terminal, and

a plurality of drain-source resistances, the plurality of the drain-source resistors being coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches;

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the first terminal and farthest from the second terminal are connected to the first terminal;

the sources of the bypass FET switches closest to the second terminal and farthest from the first terminal are connected to the second terminal;

wherein;

a first supply voltage applied to the first terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa;

a second supply voltage applied to the third terminal is configured to open the plurality of the first bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the first bypass FET switches when the plurality of the main FET switches is transitioning from the OFF to the ON state, and

a third supply voltage applied to the fourth terminal is configured to open the plurality of the second bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the second bypass FET switches when the plurality of the main FET switches is transitioning from the ON to the OFF state.

28. An amplifier comprising:

a first node;

a second node;

an input terminal;

an output terminal;

a series arrangement of a plurality of FET transistors coupled between the first node and the second node;

one or more switching blocks, each of the one or more switching blocks comprising a bypass switch coupled across a gate resistor;

wherein;

the input terminal is configured to receive an input RF signal and the output terminal is configured to provide an output RF signal;

each of the one or more switching blocks couples a control voltage to a gate of a corresponding FET transistor, wherein the control voltage is configured to transition the corresponding FET transistor from an OFF to an ON state and vice versa, and

the bypass switch of each of the one or more switching blocks is configured to open when the corresponding FET transistor is in the OFF or the ON state and to close when the corresponding FET transistor is transitioning from the OFF to the ON state and vice versa, thereby passing the corresponding gate resistor.