Timing Channel Circuitry for Creating Pulses in an Implantable Stimulator Device

• US 20180169424A1
• Filed: 02/14/2018
• Published: 06/21/2018
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Griffith, Paul J., Marnfeldt, Goran N., Parramon, Jordi
• Granted Patent: US 10,391,322 B2
• Time in Patent Office: Days
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware

Abstract

Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Claims

1. An implantable stimulator device, comprising:

a plurality of electrodes configured to provide stimulation to a patient'"'"'s tissue;

a memory configured to store pulse parameters for a periodic pulse, wherein each pulse comprises a plurality of sequential pulse phases, wherein at least one pulse phase with a first duration comprises a plurality of sequential sub-phases, wherein the at least one pulse phase has an amplitude that is not constant,

wherein data stored in the memory for each sub-phase of the at least one pulse phase comprises at least an amplitude of the sub-phase and a second duration of the sub-phase less than the first duration, wherein the amplitudes of the sub-phases are not all equal;

stimulation circuitry electrically coupled to the plurality of electrodes; and

control circuitry configured to sequentially receive the second duration for each sequential sub-phase from the memory, wherein the control circuitry is configured to sequentially provide the amplitude for each sequential sub-phase to the stimulation circuitry in accordance with the second durations to allow the stimulation circuitry to form the non-constant amplitude pulse phase at at least one of the plurality of electrodes.

2. The implantable stimulator device of claim 1, wherein the data for each sub-phase further comprises a percentage of the amplitude that each one of the plurality of electrodes is to receive.

3. The implantable stimulator device of claim 2, wherein the data for each sub-phase further comprises a polarity of the amplitude that each one of the plurality of electrodes is to receive.

4. The implantable stimulator device of claim 2, further comprising a first register, wherein the control circuitry is configured to sequentially read the amplitude and percentages for a sub-phase out of the memory to the register.

5. The implantable stimulator device of claim 4, wherein the control circuitry is configured to provide the amplitude and percentages for a sub-phase from the first register to the stimulation circuitry in parallel.

6. The implantable stimulator device of claim 4, wherein the control circuitry comprises a second register, wherein the control circuitry is configured to read the duration for a sub-phase out of the memory to the second register.

7. The implantable stimulator device of claim 6, wherein the data for each sub-phase further comprises a command that indicates that the sub-phase comprises an active phase.

8. The implantable stimulator device of claim 7, wherein the control circuitry is configured to read the command for a sub-phase out of the memory to the second register.

9. The implantable stimulator device of claim 1, wherein the data for each sub-phase is stored in a plurality of addresses of the memory.

10. The implantable stimulator device of claim 9, wherein the data for each sub-phase is stored in the same number of addresses in the memory.

11. The implantable stimulator device of claim 9, wherein plurality of addresses for each sub-phase are sequential in the memory.

12. The implantable stimulator device of claim 9, wherein the data for each sub-phase further comprises data indicative of a number of the plurality of addresses in which the sub-phase is stored.

13. The implantable stimulator device of claim 9, wherein the data for each sub-phase further comprises a starting address in which the data for a subsequent sub-phase is stored.

14. The implantable stimulator device of claim 1, wherein the non-constant amplitude increases during the at least one pulse phase.

15. The implantable stimulator device of claim 1, wherein the second duration of each of the sub-phases is equal.

16. The implantable stimulator device of claim 1, wherein the amplitude of each of the sub-phases comprises a constant current amplitude.

17. The implantable stimulator device of claim 1, wherein the stimulation circuitry comprises current source circuitry and current sink circuitry.

18. The implantable stimulator device of claim 1, wherein the stimulation circuitry is electronically coupled to each of the plurality of electrodes by a decoupling capacitor.