PARTIALLY DE-CENTRALIZED LATCH MANAGEMENT ARCHITECTURES FOR STORAGE DEVICES

• US 20180173444A1
• Filed: 02/19/2018
• Published: 06/21/2018
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation), Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Marcu, Alon, Hahn, Judah Gamliel, Vishne, Gadi, Bazarsky, Alex, Navon, Ariel
• Granted Patent: US 10,642,513 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.

Claims

1. A memory system comprising:

a controller;

non-volatile memory coupled with the controller, wherein the non-volatile memory further comprises;

a non-volatile memory array comprising a plurality of dies;

latches that are located on the dies; and

latch management circuitry that identifies one of the plurality dies as a leader die, wherein the leader die performs a data transfer to or from one or more latches from one of the dies.

2. The memory system of claim 1, wherein the data transfer comprises writing to the one or more latches when the leader die detects a write operation.

3. The memory system of claim 1, wherein the data transfer comprises reading from the one or more latches when the leader die detects a read operation.

4. The memory system of claim 1, wherein the leader die sends a busy signal to the controller for the data transfer.

5. The memory system of claim 1, wherein the latch management circuitry utilizes a suspend and resume commands, wherein a partial release command results in a faster bus response and a full release command results in a slower bus response.

6. The memory system of claim 1, wherein the leader die is one of a plurality of the die that are connected to a same bus or channel and the leader die is a leader for each of the die connected to the same bus or channel.

7. The memory system of claim 1, wherein the non-volatile memory further comprises:

a first memory bus connecting at least a portion of the dies;

a second memory bus connecting at least a different portion of the dies; and

a bridge connecting the first memory bus and the second memory bus.

8. The memory system of claim 7, wherein the leader die is a leader of both the at least a portion of the dies, and the at least a different portion of the dies.

9. The memory system of claim 7, wherein transactions are run in parallel for the portion of the dies and for the different portion of the dies.

10. The memory system of claim 1, wherein the non-volatile memory further comprises:

a first memory bus connecting at least a portion of the dies;

a second memory bus connecting at least a different portion of the dies;

a first bridge coupled with the first memory bus; and

a second bridge coupled with the second memory bus, wherein the first bridge and the second bridge are connected.

11. The memory system of claim 10, wherein the leader die is a leader of the at least a portion of the dies, and a second leader die from the at least a different portion of the dies is a leader of the at least a different portion of the dies.

12. The memory system of claim 10, wherein transactions are run in parallel for the portion of the dies and for the different portion of the dies.

13. The memory system of claim 1, wherein the leader die is loaded with a sequence of operations that the leader die can run.

14. The memory system of claim 13, wherein the sequence of operations comprises a garbage collection operation between different die located on a same bus that is managed by the leader die without the controller.

15. The memory system of claim 1, wherein the identification of the leader die is caused by an external event or is caused by the controller.

16. A memory system comprising:

a controller;

a plurality of memory dies coupled with the controller, wherein the memory dies further comprise;

cache storage on each of the memory dies for storing data; and

caching logic circuitry that is used by a leader die for managing the cache storage for a group of the dies that are connected with the leader die, wherein the managing by the leader die comprises identifying which of the cache storage is used for a data transfer.

17. The memory system of claim 16, wherein the cache storage comprises latches and the data transfer comprises writing to the latches from the group of dies when the leader die detects a write operation, and comprises reading from the latches from the group of dies when the leader die detects a read operation.

18. The memory system of claim 16, wherein the group of the dies comprises all dies connected to a same bus or channel and the leader die is connected to the same bus or channel.

19. The memory system of claim 16, wherein the group of the dies comprises a first group of dies, the memory dies further comprising:

a first memory bus connecting the first group of dies;

a second group of dies separate from the first group of dies;

a second memory bus connecting the second group of dies; and

a bridge connecting the first memory bus and the second memory bus;

wherein the leader die is a leader of both the first group of dies and the second group of dies.

20. The memory system of claim 16, wherein the group of the dies comprises a first group of dies, the memory dies further comprising:

a first memory bus connecting the first group of dies;

a second group of dies separate from the first group of dies;

a second memory bus connecting the second group of dies;

a first bridge coupled with the first memory bus; and

a second bridge coupled with the second memory bus, wherein the first bridge and the second bridge are connected;

wherein the leader die is a leader of both the first group of dies and the second group of dies.

21. The memory system of claim 16, wherein the leader die includes a sequencer for completing a sequence of operations.

22. A memory device with a controller and NAND memory, the device comprising:

means for determining a leader die from dies in the NAND memory;

means for receiving a command that includes a data transfer to or from one or more latches from the dies in the NAND memory; and

means for the leader die to manage the data transfer.