Self-Aligned Spacers and Method Forming Same

• US 20180174904A1
• Filed: 12/21/2016
• Published: 06/21/2018
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Yi-Tsang, Chao, Cha-Hsin, Chiu, Yi-Wei, Hsu, Li-Te, Hsia, Ying Ting
• Granted Patent: US 10,510,598 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Claims

1. A method comprising:

forming a bottom source/drain contact plug in a bottom inter-layer dielectric, wherein the bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor;

forming a first inter-layer dielectric overlying the bottom source/drain contact plug;

forming a first source/drain contact opening in the first inter-layer dielectric, with the bottom source/drain contact plug exposed through the first source/drain contact opening;

forming a first dielectric spacer layer, wherein the first dielectric spacer layer comprises a first portion extending into the first source/drain contact opening, and a second portion over the first inter-layer dielectric;

performing an anisotropic etching on the first dielectric spacer layer, wherein a remaining vertical portion of the first dielectric spacer layer forms a first source/drain contact spacer; and

filling a remaining portion of the first source/drain contact opening to form a first source/drain contact plug.

2. The method of claim 1 further comprising:

forming a first etch stop layer over and in contact with a gate spacer of the transistor and the bottom source/drain contact plug, wherein the first inter-layer dielectric is over and contacting the first etch stop layer.

3. The method of claim 1 further comprising:

etching the first inter-layer dielectric to form a gate contact opening;

etching a hard mask between gate spacers of the transistor to extend the gate contact opening between the gate spacers;

forming a second spacer layer having a portion extending into the gate contact opening;

etching the second spacer layer to form a gate contact spacer in the gate contact opening; and

forming a gate contact plug in the gate contact opening.

4. The method of claim 3 further comprising:

forming a second inter-layer dielectric over the first inter-layer dielectric;

etching the second inter-layer dielectric to form a second source/drain contact opening, wherein the second spacer layer further extends into the second source/drain contact opening, and the etching the second spacer layer further forms a second source/drain contact spacer in the second source/drain contact opening; and

forming a second source/drain contact plug in the second source/drain contact opening.

5. The method of claim 1 further comprising:

forming a first low-k dielectric layer over the first inter-layer dielectric;

forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source/drain region; and

forming a dielectric metal line spacer encircling the metal line.

6. The method of claim ₅ further comprising:

forming a second low-k dielectric layer over the first low-k dielectric layer;

forming a metal via in the second low-k dielectric layer, wherein the metal via is electrically coupled to the source/drain region; and

forming a dielectric via spacer encircling the metal via.

7. The method of claim 1 further comprising:

forming a sacrificial layer over a gate stack of the transistor;

etching the sacrificial layer and the bottom inter-layer dielectric to form a bottom source/drain contact opening;

forming a bottom contact spacer in the bottom source/drain contact opening;

filling the bottom source/drain contact opening with a conductive material; and

performing a planarization to remove the sacrificial layer and portions of the conductive material over the bottom inter-layer dielectric to form the bottom source/drain contact plug.

8. A method comprising:

forming a first source/drain contact plug in a first inter-layer dielectric, wherein the first source/drain contact plug is electrically coupled to a source/drain region of a transistor;

forming a second inter-layer dielectric overlying the first inter-layer dielectric;

forming a second source/drain contact plug in the second inter-layer dielectric;

forming a third inter-layer dielectric overlying the second inter-layer dielectric;

etching the second inter-layer dielectric and the third inter-layer dielectric to form a gate contact opening, wherein a gate electrode of the transistor is exposed to the gate contact opening;

forming a gate contact spacer in the gate contact opening, wherein the gate contact spacer penetrates through the second inter-layer dielectric and the third inter-layer dielectric; and

forming a gate contact plug in the gate contact opening, wherein the gate contact plug is encircled by the gate contact spacer.

9. The method of claim 8 further comprising:

etching the third inter-layer dielectric to form a source/drain contact opening, wherein the second source/drain contact plug is exposed through the source/drain contact opening;

forming a source/drain contact spacer in the source/drain contact opening; and

forming a third source/drain contact plug in the source/drain contact opening, wherein the second source/drain contact plug is encircled by the source/drain contact spacer.

10. The method of claim ₉, wherein the forming the gate contact spacer and the forming the source/drain contact spacer share a common deposition process and a common etching process.

11. The method of claim 8, wherein the forming the gate contact spacer comprises:

depositing a dielectric spacer layer extending into the gate contact opening and penetrating through the second inter-layer dielectric and the third inter-layer dielectric; and

performing an anisotropic etching on the dielectric spacer layer, wherein a remaining portion of the dielectric spacer layer forms the gate contact spacer.

12. The method of claim 8 further comprising, after the second inter-layer dielectric and the third inter-layer dielectric are etched to form the gate contact opening, etching a hard mask between gate spacers of the transistor to extend the gate contact opening between the gate spacers.

13. The method of claim 12, wherein the gate contact spacer and the gate contact plug extend to a level lower than top surfaces of the gate spacers.

14. The method of claim 8 further comprising:

forming a first low-k dielectric layer over the third inter-layer dielectric;

forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source/drain region; and

forming a dielectric metal line spacer encircling the metal line.

15. The method of claim 14 further comprising:

forming a second low-k dielectric layer over the first low-k dielectric layer;

forming a via in the second low-k dielectric layer, wherein the via is electrically coupled to the source/drain region; and

forming a dielectric via spacer encircling the via.

16-20. -20. (canceled)

21. A method comprising:

forming a replacement gate stack between two gate spacers, wherein the replacement gate stack and the two gate spacers are in a first Inter-Layer Dielectric (ILD);

forming a source/drain region on a side of the replacement gate stack;

forming a sacrificial dielectric layer over the replacement gate stack, the two gate spacers, and the first ILD;

etching the sacrificial dielectric layer and the first ILD to form a source/drain contact opening and to reveal the source/drain region;

forming contact spacers on sidewalls of the source/drain contact opening;

filling the source/drain contact opening with a conductive material; and

performing a planarization process to remove the sacrificial dielectric layer, wherein a remaining portion of the conductive material forms a first source/drain contact plug.

22. The method of claim 21 further comprising forming a hard mask overlapping the replacement gate stack, wherein the hard mask is also between the two gate spacers, and the planarization process is performed until the hard mask is exposed.

23. The method of claim 21, wherein the forming the contact spacers comprises:

depositing a blanket dielectric layer extending into the source/drain contact opening; and

performing an anisotropic etch on the source/drain contact opening.

24. The method of claim 21 further comprising:

forming a second ILD over the first ILD; and

forming a second source/drain contact plug in the second ILD, wherein the second source/drain contact plug overlaps, and is electrically coupled to, the first source/drain contact plug.

25. The method of claim 24 further comprising:

forming a third ILD over the second ILD; and

simultaneously forming a gate contact plug and a third source/drain contact plug, wherein the gate contact plug is electrically connected to the replacement gate stack, and the third source/drain contact plug overlaps, and is electrically coupled to, the second source/drain contact plug.