SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20180175138A1
• Filed: 12/11/2017
• Published: 06/21/2018
• Est. Priority Date: 12/21/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: UENO, Katsunori, TAKASHIMA, Shinya, EDO, Masaharu
• Granted Patent: US 10,374,031 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.

Claims

1. A semiconductor device comprising:

at least two isolation trench portions;

a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and

a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein

the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region, and

the mesa region and the contact layer are formed of a GaN-based semiconductor material.

2. The semiconductor device according to claim 1, wherein

the same impurities as in the contact layer are present in the source region, and

the second-conduction-type impurity concentration in the source region and the second-conduction-type impurity concentration in the contact layer provided in contact with the bottom portions of the isolation trench portions are the same.

3. The semiconductor device according to claim 1, wherein

the base region is provided covering corner portions positioned at bottom ends of side portions of the gate trench portion in contact with the base region.

4. The semiconductor device according to claim 1, wherein

the base region has a tail region in which the impurity concentration of impurities with a first conduction type, which is the same conduction type as the impurities of the source region, gradually decreases in a depth direction of the gate trench portion.

5. The semiconductor device according to claim 1, wherein

the contact layer is provided on the source region, and

the semiconductor device further comprises a source electrode having at least a portion thereof provided on the contact layer that is provided on the mesa region, and penetrating through the contact layer to contact the source region.

6. The semiconductor device according to claim 1, wherein

the second-conduction-type impurity concentration of the contact layer provided on the side portions of the mesa region and the second-conduction-type impurity concentration of the contact layer provided in contact with the bottom portions of the isolation trench portions are the same.

7. The semiconductor device according to claim 1, wherein

the second-conduction-type impurity concentration of the contact layer provided on the side portions of the mesa region is higher than the second-conduction-type impurity concentration of the contact layer provided in contact with the bottom portions of the isolation trench portions.

8. The semiconductor device according to claim 1, wherein

the contact layer has an opening on the source region, and

the contact layer contacts a top portion of the mesa region.

9. The semiconductor device according to claim 8, wherein

in a top view of the semiconductor device, an end portion of the opening of the contact layer is positioned on a side end portion of the source region.

10. The semiconductor device according to claim 8, wherein

in a top view of the semiconductor device, a position of an end portion of the opening of the contact layer matches a position of a side end portion of the source region.

11. A method of manufacturing a semiconductor device, comprising:

epitaxially forming a base region with a second conduction type on a drift region with a first conduction type;

forming a mesa region between at least two isolation trench portions, by partially etching the drift region and the base region;

epitaxially forming a contact layer that contacts a top portion of the mesa region, side portions of the mesa region, and bottom portions of the isolation trench portions, and has a second-conduction-type impurity concentration that is higher than that of the base region; and

forming a gate trench portion.

12. The method of manufacturing the semiconductor device according to claim 11, further comprising:

ion-implanting impurities with a first conduction type in a predetermined region of the contact layer provided on the top portion of the mesa region, after the epitaxially forming the contact layer and before the forming the gate trench portion.

13. The method of manufacturing the semiconductor device according to claim 11, further comprising:

epitaxially forming a source region with a first conduction type on the base region, after the epitaxially forming the base region and before the forming the mesa region.

14. The method of manufacturing the semiconductor device according to claim 11, wherein

the epitaxially forming the contact layer is performed after the forming the mesa region and before the forming the gate trench portion, and the method of manufacturing the semiconductor device further comprises:

thermally treating the contact layer, after the epitaxially forming the contact layer and before the forming the gate trench portion;

forming an opening in the contact layer, after the thermally treating the contact layer and before the forming the gate trench portion; and

ion-implanting impurities with a first conduction type in the base region via at least the opening, after the forming the opening in the contact layer and before the forming the gate trench portion.