IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS
First Claim
1. An imaging sensor comprising:
- a plurality of substrates comprising a first substrate and at least one second, subsequent supporting substrate;
a pixel array;
a plurality of interconnects; and
a plurality of support circuits;
wherein the first substrate of the plurality of substrates comprises the pixel array;
wherein the plurality of supporting circuits are disposed on the at least one second, subsequent supporting substrate that is disposed remotely relative to said first substrate;
wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array via the plurality of interconnects disposed between said first substrate and said at least one second, subsequent supporting substrate;
wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged;
wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.
1 Assignment
0 Petitions
Accused Products
Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
4 Citations
21 Claims
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1. An imaging sensor comprising:
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a plurality of substrates comprising a first substrate and at least one second, subsequent supporting substrate; a pixel array; a plurality of interconnects; and a plurality of support circuits; wherein the first substrate of the plurality of substrates comprises the pixel array; wherein the plurality of supporting circuits are disposed on the at least one second, subsequent supporting substrate that is disposed remotely relative to said first substrate; wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array via the plurality of interconnects disposed between said first substrate and said at least one second, subsequent supporting substrate; wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged; wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21-66. -66. (canceled)
Specification