ARRAY SUBSTRATE, FABRICATION METHOD THEREOF AND DISPLAY DEVICE

• US 20180233518A1
• Filed: 06/26/2015
• Published: 08/16/2018
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Qing, Haigang, Qi, Xiaojing
• Granted Patent: US 10,418,383 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

An array substrate, a fabrication method thereof, and a display device are provided. The array substrate includes a base substrate (1), a thin film transistor (2) over the base substrate (1), a first common electrode (3) over the base substrate (1), a pixel electrode (4) over the first common electrode (3) and being electrically insulated from the first common electrode (3), and a second common electrode (5) disposed over the pixel electrode (4) and being electrically insulated from the pixel electrode (4). The pixel electrode (4) is electrically connected to a drain electrode (10) of the thin film transistor (2).

Claims

1. An array substrate, comprising:

a base substrate;

a thin film transistor over the base substrate;

a first common electrode over the base substrate;

a pixel electrode over the first common electrode and being electrically insulated from the first common electrode; and

a second common electrode disposed over the pixel electrode, and being electrically insulated from the pixel electrode, wherein the pixel electrode is electrically connected to a drain electrode of the thin film transistor.

2. The array substrate of claim 1, wherein the thin film transistor includes:

a gate electrode over a first surface portion of the base substrate, wherein the first common electrode is over a second surface portion of the base substrate,

a first insulating layer having a first portion over the gate electrode,

an active layer over the first portion of the first insulating layer, and

a source electrode and the drain electrode both over the active layer.

3. The array substrate of claim 2, wherein:

the first insulating layer has a second portion over the first common electrode, and

the pixel electrode is over the second portion of the first insulating layer and electrically insulated from the first common electrode.

4. The array substrate of claim 2, further including:

a second insulating layer over the drain electrode and over the first common electrode,

wherein;

the pixel electrode is over the second insulating layer, the pixel electrode having a portion passing through the second insulating layer to electrically connect to the drain electrode, and

the first and the second insulating layers are between the first common electrode and the pixel electrode.

5. The array substrate of claim 1, further including:

a third insulating layer formed over the pixel electrode, wherein the second common electrode is formed over the third insulating layer.

6. The array substrate of claim 5, wherein the first common electrode is a slit-shaped electrode or a plate-shaped electrode.

7. The array substrate of claim 5, wherein the second common electrode is a slit-shaped electrode.

8. The array substrate of claim 5, wherein the pixel electrode on a display area of the array substrate has a vertical direction projection to cover the first common electrode.

9. The array substrate of claim 1, wherein the first and the second common electrodes are both connected to a common electrode line in a non-display area arranged in an edge region of the array substrate.

10. The array substrate of claim 1, wherein the first and the second common electrodes are configured to have a substantially same electric potential.

11. A display device, comprising the array substrate of claim 1.

12. A method for fabricating an array substrate, comprising:

providing a base substrate;

forming a thin film transistor over the base substrate;

forming a first common electrode over the base substrate;

forming a pixel electrode over the first common electrode and electrically insulated from the first common electrode; and

forming a second common electrode over the pixel electrode and electrically insulated from the pixel electrode, wherein the pixel electrode is electrically connected to a drain electrode of the thin film transistor.

13. The method of claim 12, wherein the thin film transistor is formed by:

forming a gate electrode over a first surface portion of the base substrate,

forming a first insulating layer having a first portion over the gate electrode,

forming an active layer over the first portion of the first insulating layer, and

forming a source electrode and the drain electrode over the active layer.

14. The method of claim 13, wherein:

the first common electrode is formed over a second surface portion of the base substrate.

15. The method of claim 12, further including:

forming the pixel electrode over a second portion of the first insulating layer that is formed over the first common electrode, and

forming the drain electrode over the active layer.

16. The method of claim 15, wherein a top surface the drain electrode is higher than a top surface of the pixel electrode.

17. The method of claim 12, further including:

forming a second insulating layer over the drain electrode and over the first common electrode,

wherein;

the pixel electrode is formed over the second insulating layer, the pixel electrode having a portion passing through the second insulating layer to electrically connect to the drain electrode, and

the first and the second insulating layers are formed between the first common electrode and the pixel electrode.

18. The method of claim 12, further including:

forming a third insulating layer over the pixel electrode, wherein the second common electrode is formed over the third insulating layer.

19. The method of claim 12, wherein the first and the second common electrodes are configured to have a substantially same electric potential.