ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF

• US 20180233519A1
• Filed: 02/28/2017
• Published: 08/16/2018
• Est. Priority Date: 07/18/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Choi, Seungjin
• Granted Patent: US 10,700,097 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.

Claims

1. An array substrate having a display area and a peripheral area, comprising:

a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and

a plurality of second thin film transistors in the peripheral area;

wherein an oxygen content in active layers of the plurality of first thin film transistors is higher than that in active layers of the plurality of second thin film transistors.

2. The array substrate of claim 1, wherein initial threshold voltages of the plurality of first thin film transistors are more positive or less negative than initial threshold voltages of the plurality of second thin film transistors.

3. The array substrate of claim 1, wherein the active layers of the plurality of first thin film transistors and the active layers of the plurality of second thin film transistors comprise MlO_aN_b, wherein Ml is a single metal or a combination of metals, a>

0, and b≥

0.

4. The array substrate of claim 3, wherein the active layers of the plurality of first thin film transistors and the active layers of the plurality of second thin film transistors comprise indium gallium zinc oxide.

5. The array substrate of claim 3, wherein the plurality of first thin film transistors and the plurality of second thin film transistors are bottom gate-type thin film transistors;

each of the plurality of first thin film transistors comprises a gate electrode on a side of each of the active layers of the plurality of first thin film transistors proximal to the base substrate; and

each of the plurality of second thin film transistors comprises a gate electrode on a side of each of the active layers of the plurality of second thin film transistors proximal to the base substrate.

6. The array substrate of claim 1, wherein channel regions, source electrode contact regions, and drain electrode contact regions of the active layers of the plurality of first thin film transistors have substantially a same oxygen content;

and

channel regions, source electrode contact regions, and drain electrode contact regions of the active layers of the plurality of second thin film transistors have substantially a same oxygen content.

7. The array substrate of claim 1, wherein the plurality of second thin film transistors are in one or more gate-on-array circuits.

8. The array substrate of claim 1, wherein a ratio of the oxygen content in active layers of the plurality of first thin film transistors to that in active layers of the plurality of second thin film transistors is in a range of approximately 1.005 to approximately 1.2.

9. A method of fabricating an array substrate having a display area and a peripheral area, comprising:

forming a plurality of first thin film transistors respectively in a plurality of subpixels in the display area and a plurality of second thin film transistors in the peripheral area;

wherein the plurality of first thin film transistors are formed to have a higher oxygen content in active layers of the plurality of first thin film transistors than that in active layers of the plurality of second thin film transistors.

10. The method of claim 9, comprising:

forming a semiconductor material layer on a base substrate;

patterning the semiconductor material layer to form a plurality of first semiconductor material blocks corresponding to the active layers of the plurality of first thin film transistors and a plurality of second semiconductor material blocks corresponding to the active layers of the plurality of second thin film transistors; and

increasing an oxygen content in the plurality of first semiconductor material blocks.

11. The method of claim 10, wherein increasing the oxygen content in the plurality of first semiconductor material blocks is performed by plasma bombarding the plurality of first semiconductor material blocks with a plasma comprising oxygen.

12. The method of claim 11, wherein the plasma comprising oxygen comprises nitrous oxide or oxygen.

13. The method of claim 11, wherein the plasma bombarding is performed at a power in a range of approximately 400 w to approximately 800 w for a duration in a range of approximately 40 seconds to approximately 60 seconds.

14. The method of claim 10, wherein patterning the semiconductor material layer to form the plurality of first semiconductor material blocks and the plurality of second semiconductor material blocks are performed in a single process.

15. The method of claim 14, wherein patterning the semiconductor material layer comprises:

forming a first photoresist layer on a side of the semiconductor material layer distal to the base substrate;

the first photoresist layer being in a first region corresponding to the active layers of the plurality of first thin film transistors and the active layers of the plurality of second thin film transistors;

removing the semiconductor material layer outside the first region, thereby forming the plurality of first semiconductor material blocks and the plurality of second semiconductor material blocks;

forming a second photoresist layer by removing a portion of the first photoresist layer to expose the plurality of first semiconductor material blocks, the second photoresist layer being on a side of the plurality of second semiconductor material blocks distal to the base substrate;

wherein increasing the oxygen content in the plurality of first semiconductor material blocks comprises plasma bombarding the plurality of first semiconductor material blocks with a plasma comprising oxygen, thereby forming the active layers of the plurality of first thin film transistors; and

subsequent to increasing the oxygen content in the plurality of first semiconductor material blocks, the method further comprising removing the second photoresist layer thereby forming the active layers of the plurality of second thin film transistors.

16. The method of claim 14, wherein patterning the semiconductor material layer comprises:

forming a photoresist material layer on a side of the semiconductor material layer distal to the base substrate;

exposing the photoresist material layer with a mask plate, and developing an exposed photoresist material layer to obtain a photoresist pattern having a first section in a region corresponding to the active layers of the plurality of first thin film transistors and the active layers of the plurality of second thin film transistors, and a second section outside of the first region, the photoresist material being removed in the second section thereby forming a first photoresist layer in the second section; and

removing the semiconductor material layer in a region corresponding to the second section, thereby forming the plurality of first semiconductor material blocks and the plurality of second semiconductor material blocks.

17. The method of claim 16, wherein the mask plate is a half-tone mask plate or a gray-tone mask plate, the first section comprises a first zone and a second zone;

the first zone corresponding to the active layers of the plurality of first thin film transistors;

the second zone corresponding to the active layers of the plurality of second thin film transistors;

the second zone is substantially unexposed, the first zone is partially exposed, and the second section is fully exposed; and

the first photoresist layer in the second zone has a thickness greater than that in the first zone;

the method further comprising;

ashing the first photoresist layer to remove the first photoresist layer in the first zone thereby exposing the plurality of first semiconductor material blocks;

wherein photoresist material in the second zone remains with a reduced thickness subsequent to ashing, thereby forming a second photoresist layer.

19. The method of claim 9, wherein the active layers of the plurality of first thin film transistors and the active layers of the plurality of second thin film transistors comprise MlO_aN_b, wherein M1 is a single metal or a combination of metals, a>

0, and b≥

0.

20. An array substrate fabricated by a method of claim 9.

21. A display apparatus, comprising the array substrate of claim 20.

18. (canceled)