DUAL CHANNEL FINFETS HAVING UNIFORM FIN HEIGHTS

• US 20180240714A1
• Filed: 11/14/2017
• Published: 08/23/2018
• Est. Priority Date: 02/17/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Xu, Peng, Yang, Jie
• Granted Patent: US 10,546,788 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 21/2205 from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/228 using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8254 the substrate being a semiconductor, using II-VI technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 : characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 : with rounded corners

Abstract

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first blanket layer on a substrate;

forming a second blanket layer on the first blanket layer;

patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer;

depositing a mask on the second transistor region;

removing the first fin to form a trench;

growing a first semiconductor layer in the trench where the first fin was removed; and

growing a second semiconductor layer on the first semiconductor layer.

2. The method of claim 1, wherein the first blanket layer comprises a dopant, the dopant being an n-type dopant or a p-type dopant.

3. The method of claim 1, further comprising performing an epitaxial prebake process before growing a first semiconductor layer in the trench.

4. The method of claim 1, further comprising depositing a dielectric material on and around the first fin and the second fin before depositing the mask.

5. The method of claim 4, further comprising depositing a hardmask on the second blanket epitaxial layer before patterning the first fin and the second fin.

6. The method of claim 5, further comprising recessing the second semiconductor layer and the dielectric material, and removing the hardmask before depositing a gate on the first fin and the second fin.

7. The method of claim 1, wherein the first semiconductor layer comprises p-doped silicon.

8. The method of claim 1, wherein the first blanket layer comprises n-doped silicon.

9. A method of making a semiconductor device, the method comprising:

forming a blanket layer of n-doped silicon on a silicon substrate;

forming a blanket layer of SiGe on the blanket layer of n-doped silicon;

patterning a first fin of an n-type field effect transistor (NFET) and a second fin of a p-type field effect transistor (PFET) in the blanket layer of n-doped silicon and the blanket layer of SiGe;

depositing a mask on the second fin of the PFET;

depositing a dielectric material around the first fin and the second fin;

removing the first fin to form a trench in the dielectric material;

performing an epitaxial prebake process to round a bottom edge of the trench;

growing a p-doped silicon epitaxial layer in the trench where the first fin was removed; and

growing a silicon epitaxial layer on the p-doped epitaxial layer.

10. The method of claim 9, further comprising polishing a surface of the dielectric material after growing the silicon epitaxial layer to remove silicon overgrowth.

11. The method of claim 10, further comprising recessing the silicon epitaxial layer and the dielectric material to form silicon fins in the NFET.

12. The method of claim 11, wherein the second fin of the PFET further comprises a hardmask cap, and the method further comprises removing the hardmask cap after growing the silicon epitaxial layer.

13. The method of claim 9, further comprising forming a gate stack on the first fin and the second fin.

14. The method of claim 13, wherein the gate stack comprises a gate dielectric layer deposited directly on the silicon epitaxial layer of the first fin and the blanket layer of SiGe of the second fin.