HIGH SPEED TRI-LEVEL INPUT POWER CONVERTER GATE DRIVER

• US 20180254703A1
• Filed: 05/07/2018
• Published: 09/06/2018
• Est. Priority Date: 08/29/2016
• Status: Active Grant

• Current Assignee: Silanna Asia Pte. Ltd.
• Original Assignee: Silanna Asia Pte. Ltd.
• Inventors: Newlin, Trevor M.
• Granted Patent: US 10,243,462 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various methods and devices that involve electronic circuits are disclosed. A disclosed method includes buffering an input signal using a first buffer. The first buffer is powered by a supply voltage and a reference voltage. The method also includes buffering the input signal using a second buffer. The second buffer is powered by the reference voltage and a ground voltage. The method also includes level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, and level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter. The voltage range is larger than a delta between the supply voltage and the reference voltage. The reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage.

Claims

1. A control circuit comprising:

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range; and

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

wherein the voltage range is larger than a delta between the supply voltage and the reference voltage; and

wherein the reference voltage is greater than the ground voltage and less than the supply voltage.

2. The control circuit of claim 1, wherein:

the first level shifter is powered by the supply voltage and the ground voltage; and

the second level shifter is powered by the supply voltage and the ground voltage.

3. The control circuit of claim 2, wherein the first and second level shifters each individually comprise:

a first circuit branch coupled between the supply voltage and the ground voltage;

a first field effect transistor located on the first circuit branch and having a first control gate;

a second circuit branch coupled between the supply voltage and the ground voltage;

a second field effect transistor located on the second circuit branch and having a second control gate; and

an internal inverter having an internal inverter input coupled to the first control gate and an internal inverter output coupled to the second control gate.

4. The control circuit of claim 1, further comprising:

a common control circuit input, wherein the common control circuit input is coupled to the first input and the second input;

a high side control circuit output, wherein an output of the first level shifter is the high side control circuit output; and

a low side control circuit output, wherein an output of the second level shifter is the low side control circuit output.

5. The control circuit of claim 4, further comprising:

a logic circuit communicatively coupled to the high side control circuit output and the low side control circuit output; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the logic circuit output is true when the high side control circuit output and the low side control circuit output are both false.

6. The control circuit of claim 1, wherein the first buffer and the second buffer each individually comprise:

a two-device complementary field effect transistor (“

FET”

) inverter;

wherein the two-device complementary FET inverter of the first buffer trips at about one half of the delta between the supply voltage and the reference voltage; and

wherein the two-device complementary FET inverter of the second buffer trips at about one half of the delta between the reference voltage and the ground voltage.

7. The control circuit of claim 6, wherein:

the two-device complementary FET inverter of the first buffer trips when the first input is equal to about three quarters of the supply voltage; and

the two-device complementary FET inverter of the second buffer trips when the second input is equal to about one quarter of the supply voltage.

8. A power converter comprising:

a control loop that regulates an output of the power converter using a switching circuit, wherein the switching circuit is coupled between an input side of the power converter and a load side of the power converter;

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range; and

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

wherein the first level shifter and the second level shifter are on the control loop;

wherein the voltage range is larger than a delta between the supply voltage and the reference voltage; and

wherein the reference voltage is greater than the ground voltage and less than the supply voltage.

9. The power converter of claim 8, further comprising:

the first level shifter is powered by the supply voltage and the ground voltage; and

the second level shifter is powered by the supply voltage and the ground voltage.

10. The power converter of claim 8, wherein the switching circuit further comprises:

a high side power field effect transistor with a high side gate node; and

a low side power field effect transistor with a low side gate node;

wherein the high side power field effect transistor is coupled to the input side of the power converter and the low side power field effect transistor;

wherein the low side power field effect transistor is coupled to the high side power field effect transistor and a power ground voltage;

wherein the first level shifter produces a high side drive signal for the high side gate node; and

wherein the second level shifter produces a low side drive signal for the low side gate node.

11. The power converter of claim 10, further comprising:

a high side gate driver circuit powered by a boosted voltage supply, and coupled to the high side gate node, wherein the high side gate driver drives the high side power field effect transistor using the high side drive signal;

a low side gate driver circuit biased by the power ground voltage, and coupled to the low side gate node, wherein the low side gate driver drives the low side power field effect transistor using the low side drive signal;

a high side latch communicatively coupled to the high side gate driver and the first level shifter, wherein the high side latch latches the high side drive signal; and

a low side latch communicatively coupled to the low side gate driver and the second level shifter, wherein the low side latch latches the low side drive signal.

12. The power converter of claim 10, further comprising:

a common control circuit input on the control loop, wherein the common control circuit input is coupled to the first input and the second input;

wherein the high side drive signal and the low side drive signal are both based on a first pulse width modulated signal received on the common control circuit input; and

wherein the high side drive signal and the low side drive signal are second and third pulse width modulated signals.

13. The power converter of claim 12, wherein:

a logic circuit communicatively coupled to the first level shifter and the second level shifter; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the high side power field effect transistor and the low side power field effect transistor are both turned off when the logic circuit output is true.

14. The power converter of claim 12, wherein the first and second level shifters each individually comprise:

a first circuit branch coupled between the supply voltage and the ground voltage;

a first field effect transistor located on the first circuit branch and having a first control gate;

a second circuit branch coupled between the supply voltage and the ground voltage;

a second field effect transistor located on the second circuit branch and having a second control gate; and

an internal inverter having an internal inverter input coupled to the first control gate and an internal inverter output coupled to the second control gate.

15. A method comprising:

buffering an input signal using a first buffer, wherein the first buffer is powered by a supply voltage and a reference voltage;

buffering the input signal using a second buffer, wherein the second buffer is powered by the reference voltage and a ground voltage;

level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter; and

level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter;

wherein the voltage range is larger than a delta between the supply voltage and the reference voltage; and

wherein the reference voltage is greater than the ground voltage and less than the supply voltage.

16. The method of claim 15, further comprising:

regulating a load using a high side power field effect transistor, a low side power field effect transistor, and a control loop;

generating a high side drive signal via at least the level shifting of the first buffer output signal;

generating a low side drive signal via at least the level shifting of the second buffer output signal;

driving the high side power field effect transistor using the high side drive signal; and

driving the low side power field effect transistor using the low side drive signal;

wherein the input signal is on the control loop.

17. The method of claim 16, further comprising:

generating a logic circuit output using a logic circuit, wherein the logic circuit is communicatively coupled to the first level shifter and the second level shifter;

delaying the logic circuit output using a delay circuit with a delay of at least 5 nanoseconds to produce a delayed logic circuit output;

generating a trilevel output signal if the delayed logic circuit output stays true for greater than 5 nanoseconds;

altering a characteristic of the control loop using the trilevel output signal.