FUNCTION CALLBACK MECHANISM BETWEEN A CENTRAL PROCESSING UNIT (CPU) AND AN AUXILIARY PROCESSOR

• US 20180267844A1
• Filed: 11/24/2015
• Published: 09/20/2018
• Est. Priority Date: 12/18/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LEWIS, BRIAN T., BARIK, RAJKISHORE, SHPEISMAN, TATIANA
• Granted Patent: US 10,255,122 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2209/548 Queue
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/547 Remote procedure calls [RPC]; Web services
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

Claims

1-25. -25. (canceled)

26. A system for implementing a function between a first processor and a second processor, said system comprising:

a shared virtual memory (SVM) coupled to the first and second processors, said SVM to store at least one double-ended queue (Deque);

an execution unit (EU) of the first processor, said EU associated with a first of the Deques, to push the function to said first Deque; and

a request handler thread executing on said second processor to;

pop the function from the first Deque;

execute the function; and

generate a completion signal to said EU in response to completion of the function.

27. The system of claim 26, wherein the function is a callback request comprising:

a function pointer to specify said function to be executed by said second processor; and

an argument pointer to specify a location in said SVM for data to be provided to said executed function and for results generated by said executed function to be provided to said EU.

28. The system of claim 26, wherein said request handler thread is further to pop the function from a second Deque, said second Deque associated with a second EU, in response to detecting that said first Deque is empty.

29. The system of claim 26, wherein said Deques are pinned in said SVM to prevent page faults in response to access attempts by said EUs and said request handlers.

30. The system of claim 26, wherein said completion signal is to set a completion flag in said SVM and said EU is further to poll said completion flag.

31. The system of claim 26, wherein said completion signal is to trigger a continuation kernel on said EU, said continuation kernel to restore previously saved stack variables.

32. The system of claim 27, wherein said request handler thread is further to sleep in response to failure to pop the callback request from any of said Deques.

33. The system of claim 32, wherein said sleep comprises execution of a Monitor/Mwait instruction.

34. The system of claim 26, wherein said first processor is a Graphics Processor Unit (GPU) and said second processor is a general purpose Central Processor Unit (CPU).

35. A method for function operation between a first processor and a second processor, said method comprising:

pushing the function, by an execution unit (EU) of said first processor, to a first double-ended queue (Deque), said Deque stored in a shared virtual memory (SVM) coupled to said first and second processors;

popping the function from said first Deque, by a request handler thread executing on said second processor;

executing, by said request handler thread, the function; and

generating, by said request handler thread, a completion signal to said EU in response to completion of said function.

36. The method of claim 35, wherein the function is a callback request comprising:

a function pointer to specify said function to be executed by said second processor; and

an argument pointer to specify a location in said SVM for data to be provided to said executed function and for results generated by said executed function to be provided to said EU.

37. The method of claim 35, further comprising popping, by said request handler thread, the function from a second Deque, said second Deque associated with a second EU, in response to detecting that said first Deque is empty.

38. The method of claim 35, further comprising pinning said Deques in said SVM to prevent page faults in response to access attempts by said EUs and said request handlers.

39. The method of claim 35, wherein generating said completion signal further comprises setting a completion flag in said SVM for polling by said EU.

40. The method of claim 35, wherein generating said completion signal further comprises triggering a continuation kernel on said EU, said continuation kernel to restore previously saved stack variables.

41. The method of claim 36, further comprising sleeping, by said request handler thread, in response to a failure to pop the callback request from any of said Deques.

42. The method of claim 41, wherein said sleeping further comprises execution of a Monitor/Mwait instruction.

43. At least one computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for a function between a first processor and a second processor, said operations comprising:

pushing the function, by an execution unit (EU) of said first processor, to a first double-ended queue (Deque), said Deque stored in a shared virtual memory (SVM) coupled to said first and second processors;

popping the function from said first Deque, by a request handler thread executing on said second processor;

executing, by said request handler thread, the function; and

generating, by said request handler thread, a completion signal to said EU in response to completion of said function.

44. The computer-readable storage medium of claim 43, wherein the function is a callback request comprising:

a function pointer to specify said function to be executed by said second processor; and

an argument pointer to specify a location in said SVM for data to be provided to said executed function and for results generated by said executed function to be provided to said EU.

45. The computer-readable storage medium of claim 43, further comprising popping, by said request handler thread, the function from a second Deque, said second Deque associated with a second EU, in response to detecting that said first Deque is empty.

46. The computer-readable storage medium of claim 43, further comprising pinning said Deques in said SVM to prevent page faults in response to access attempts by said EUs and said request handlers.

47. The computer-readable storage medium of claim 43, wherein generating said completion signal further comprises setting a completion flag in said SVM for polling by said EU.

48. The computer-readable storage medium of claim 43, wherein generating said completion signal further comprises triggering a continuation kernel on said EU, said continuation kernel to restore previously saved stack variables.

49. The computer-readable storage medium of claim 44, further comprising sleeping, by said request handler thread, in response to a failure to pop the callback request from any of said Deques.

50. The computer-readable storage medium of claim 49, wherein said sleeping further comprises execution of a Monitor/Mwait instruction.