Supply-Voltage Control for Device Power Management

• US 20180275743A1
• Filed: 04/10/2018
• Published: 09/27/2018
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Swarna, Madhu, Raja, Tezaswi
• Granted Patent: US 10,386,916 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage oldie logic below the operational supply-voltage threshold hut above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more, of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.

Claims

1. A method for reducing leakage current in logic having an operational supply voltage threshold for maintaining operation, a nonzero data-retention supply-voltage threshold for retaining data, and two or more on-die transistor switches to switchably connect a voltage source to the logic the method comprising:

after the logic enters an idle period, opening one or more of the switches to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold; and

when the logic exits the idle period, closing one or more of the switches to raise the supply voltage of the logic above the operational supply-voltage threshold.

2. The method of claim 1 wherein the one or more switches are opened when a period of inactivity in the logic exceeds an inactivity threshold.

3. The method of claim 2 further comprising adjusting the inactivity threshold according to a heuristic.

4. The method of claim 1 wherein the one or more switches are closed when a function or service of the logic is requested.

5. The method of claim 1 wherein the data retained in the logic includes a state of one or more of a register file, a cache, and a bit flag.

6. The method of claim 1 wherein the transistor switches are arranged in parallel, switchably connecting the logic to the voltage source.

7. The method of claim 6 wherein opening and closing the one or more transistor switches includes addressing the transistor switches in a two or more groups that share a common control line.

8. The method of claim 7 wherein opening and closing the one or more transistor switches includes distributing groups of closed switches uniformly over the logic.

9. The method of claim 7 wherein the two or more groups are addressed in sequence, separated by a settling period during which the supply voltage is allowed to settle before advancing to a lower or higher value.

10. The method of claim 6 further comprising determining a number of transistor switches to open or close.

11. The method of claim 1 wherein the idle period is a first idle period, the method further comprising:

after the logic enters a second idle period longer than the first, lowering the supply voltage below the data-retention supply-voltage threshold; and

when the logic exits the second idle period, raising the supply voltage above the operational supply-voltage threshold.

12. A logic-device component exhibiting reduced leakage current, the circuit comprising:

logic having an operational supply-voltage threshold for maintaining operation and a data-retention supply-voltage threshold for retaining data;

arranged in parallel, two or more transistor switches switchably connecting a voltage supply line to the logic, each switch having a gate terminal to control whether the switch is open or closed; and

a power-management unit operatively coupled to the gate terminal of each switch and configured to open one or more of the switches to lower a voltage supplied to the logic component after the component enters an idle period, bat to maintain the voltage above the data-retention supply-voltage threshold.

13. The component of claim 12, wherein the power-management unit is configured to lower the voltage supplied to the logic below the operational supply-voltage threshold.

14. The component of claim 12, wherein the power-management unit is further configured to close one or more of the switches to raise the voltage above the operational supply-voltage threshold when the component exits the idle period.

15. The component of claim 12, wherein the power-management unit is configured to lower the supply voltage when a period of component inactivity exceeds an inactivity threshold, and to raise the supply voltage when a function or service of the component is requested.

16. The component of claim 12, wherein the transistor switches include field-effect transistors.

17. The component of claim 12, wherein the transistor switches are distributed over the logic and grouped into a plurality of zones, each zone supplying power to a nearest region of the logic.

18. The component of claim 12 wherein the logic, the two or more transistor switches, and the power-management unit are arranged on the same die.

20. The component of claim 16, wherein the power-management unit is configured to close all zones of switches when the component exits the idle period, to raise the supply voltage above the operational supply-voltage threshold.

19. A logic-device component exhibiting reduced leakage current, the component comprising:

logic having an operational supply-voltage threshold for maintaining operation and a data-retention supply-voltage threshold for retaining data;

distributed over the logic, two or more zones of transistor switches, the switches of each, zone connected in parallel with gate terminals connected to a common control line, each zone switchably connecting a voltage supply line to a nearest region of the logic; and

a power-management unit operatively coupled to the control line of each zone and configured to open one or more zones of switches to lower the voltage supplied to the logic after the component enters an idle period, but to maintain the voltage above the data-retention supply-voltage threshold.