MEMORY MODULE WITH DATA BUFFERING

• US 20180300267A1
• Filed: 12/28/2017
• Published: 10/18/2018
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Solomon, Jeffrey C., Bhakta, Jayesh R.
• Granted Patent: US 10,489,314 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

Claims

1. A memory module operable in a computer system to communicate data with a memory controller of the computer system via a data bus in response to memory commands received from the memory controller, the memory commands including a first memory command and a subsequent second memory command, the first memory command to cause the memory module to receive or output at least one first data signal and the second memory command to cause the memory module to receive or output at least one second data signal, the memory module comprising:

a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system;

a plurality of memory integrated circuits mounted on the printed circuit board and arranged in a plurality of ranks including a first rank and a second rank, each rank of the plurality of ranks having a same bit width as the memory module, the plurality of memory integrated circuits including at least one first memory integrated circuit in the first rank and at least one second memory integrated circuit in the second rank, wherein the first rank is selected to receive or output the at least one first data signal in response to the first memory command and is not selected to communicate data with the memory controller in response to the second memory command, and wherein the second rank is selected to receive or output the at least one second data signal in response to the second memory command and is not selected to communicate data with the memory controller in response to the first memory command;

a data buffer coupled between the at least one first memory integrated circuit and the data bus, and between the at least one second memory integrated circuit and the data bus; and

logic coupled to the data buffer and configured to respond to the first memory command by providing first control signals to the data buffer to enable communication of the at least one first data signal between the at least one first memory integrated circuit and the memory controller through the data buffer, wherein the logic is further configured to respond to the second memory command by providing second control signals to the data buffer to enable communication of the at least one second data signal between the at least one second memory integrated circuit and the memory controller through the data buffer;

wherein the memory module has an overall CAS latency greater than an actual operational CAS latency of each of the plurality of memory integrated circuits.

2. The memory module of claim 1, wherein the data buffer is configured to isolate both the at least one first memory integrated circuit and the at least one second memory integrated circuit from the data bus when the memory module is not being accessed by the memory controller.

3. The memory module of claim 1, wherein the first memory command includes a first set of chip select signals and the second memory command includes a second set of chip select signals that are different from the first set of chip select signals.

4. The memory module of claim 1, wherein the first memory command includes at least first chip select signal and the second memory command includes at least one second chip select signal, wherein the memory module produces at least third and fourth chip select signals in response to the first memory command, the third chip select signal being provided to the at least one first memory integrated circuit and having an active value to cause the at least one first memory integrated circuit to receive or output data signals in response to the first memory command, the fourth chip-select signal being provided to the at least one second memory integrated circuit and having a non-active value to keep the at least one second memory integrated circuit from receiving or outputting data signals in response to the first memory command.

5. The memory module of claim 4, wherein the memory module produces at least fifth and sixth chip select signals in response to the second memory command, the fifth chip select signal being provided to the at least one first memory integrated circuit and having a non-active value to keep the at least one first memory integrated circuit from receiving or outputting data signals in response to the first memory command, the sixth chip select signal being provided to the at least one second memory integrated circuit and having an active value to cause the at least one second memory integrated circuit to receive or output data signals in response to the second memory command.

6. The memory module of claim 1, wherein the first memory command is a first read command and the second memory command is a second read command, wherein the first read command and the second read command are back to back adjacent read commands, and wherein the memory module outputs the at least one first data signal together with at least one first data strobe signal in response to the first read command, wherein memory module outputs the at least one second data signal together with at least one second data strobe signal in response to the second read command, wherein the at least one second data signal follows the at least one first data signal on the data bus, and wherein the data buffer is configured to prevent the at least one first data strobe signal and the at least one second data strobe signal from colliding with each other.

7. The memory module of claim 6, wherein each of the at least one first data strobe signal and the at least one second data strobe signal includes a pre-amble interval and a post-amble interval, and wherein the data buffer is configured to combine the at least one first data strobe signal and the at least one second data strobe signal into a combined burst of data strobe signals that does not include the post-amble interval of the at least one first data strobe signal and the pre-amble interval of the at least one second data strobe signal.

8. The memory module of claim 1, further comprising an SPD device that reports an overall CAS latency of the memory module to the memory controller, the overall CAS latency having one more clock cycle than an actual operational CAS latency of each of the plurality of memory integrated circuits.

9. The memory module of claim 1, wherein the memory module is further coupled to the memory controller using an on-die-termination (ODT) bus, wherein each of the plurality of memory devices includes an ODT circuit, the memory module further comprising a termination circuit external to any of the plurality of memory devices, wherein the termination circuit is coupled to the ODT bus and to the ODT circuit of at least one of the plurality of memory devices, wherein the termination circuit is configured to provide external termination of the at least one of the plurality of memory devices in response to an ODT signal on the ODT bus, and wherein the ODT circuit of the at least one of the plurality of memory devices is disabled.

10. The memory module of claim 1, wherein the data buffer comprises combinatorial logic, registers, and logic pipelines, and is configured to register an additional clock cycle for transferring the at least one first data signal or the at least one second data signal through the data buffer.

11. The memory module of claim 1, wherein the logic is further configured to determine the overall CAS latency.

12. The memory module of claim 11, wherein the logic is further configured to enable the communication of the at least one second data signal between the at least one second memory integrated circuit and the memory controller in accordance with the overall CAS latency.