MEMORY DEVICES HAVING SPECIAL MODE ACCESS

• US 20180301175A1
• Filed: 06/20/2018
• Published: 10/18/2018
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T., Tsai, Victor Y.
• Granted Patent: US 10,192,591 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Claims

1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:

a command field of the serial message configured to enable the serial interface controller to access the register;

a register address field of the serial message immediately following the command field indicating an address of the register; and

a data field of the serial message immediately following the register address field.

2. The memory device of claim 1, wherein the serial interface controller is configured to receive the serial message, wherein the command field of the serial message comprises a command that the serial interface controller is configured to interpret as enabling write access to a special mode enable register of the memory device.

3. The memory device of claim 2, wherein the serial interface controller is configured to receive the serial message, wherein the address of the register is configured to identify the special mode enable register.

4. The memory device of claim 3, wherein the serial interface controller is configured to receive the serial message, wherein the data field of the serial message comprises data to be written into the special mode enable register that is configured, when written into the special mode enable register, to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.

5. The memory device of claim 1, wherein the serial interface controller is configured to receive the serial message, wherein the command field has a size of one byte, the register address has a size of one byte, and the data field has a size of one byte.

6. A system comprising:

a master device configured to generate a clock signal; and

a memory device configured to interface with the master device using a serial peripheral interface protocol, wherein the memory device comprises a controller;

wherein the master device is configured to;

enable the controller;

send the clock signal to the controller;

send a message to the controller, wherein the message comprises;

a command field of the message configured to enable the controller to access volatile memory registers of the memory device;

a register address field of the message immediately following the command field indicating an address of a volatile memory register of the volatile memory registers; and

a data field of the message immediately following the register address field;

wherein the controller is configured to access the volatile memory registers of the memory device that control operation of a memory array by storing bits in response to receiving the message from the master device.

7. The system of claim 6, wherein the controller is configured to send a synchronous message in response to receiving the message from the master device.

8. The system of claim 6, wherein the master device is configured to enable the controller by setting a chip select input pin of the memory device to low.

9. The system of claim 6, wherein the controller is configured to interpret the command field as enabling write access to a special mode enable register of the memory device.

10. The system of claim 9, wherein the controller is configured to interpret the address as identifying the special mode enable register.

11. The system of claim 10, wherein the controller is configured to write data in the data field to the special mode enable register, wherein when the controller writes the data to the special mode enable register, the memory device operates according to a special mode of operation.

12. A memory device, comprising:

a serial interface controller;

a register coupled to the serial interface controller; and

a memory array coupled to the serial interface controller, wherein the serial interface controller is configured to receive and operate using a serial message comprising a command field configured to enable the serial interface controller to access the register, a register address field immediately following the command field indicating an address of the register, and a data field immediately following the register address field to access the register that controls operation of the memory array by storing bits.

13. The memory device of claim 12, wherein the serial interface controller is configured to interpret a command in the command field as enabling write access to a special mode enable register of the memory device.

14. The memory device of claim 12, wherein the serial interface controller is configured to identify a special mode enable register based on the address in the register address field.

15. The memory device of claim 12, wherein the serial interface controller is configured to write data of the data field into a special mode enable register to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.

16. The memory device of claim 15, wherein the one time programmable (OTP) access mode is configured to enable the memory device to perform operations on nonvolatile memory of the memory device.

17. The memory device of claim 15, wherein the parameter page access mode is configured to enable the memory device to read parameter page contents from a page of memory of a NAND memory array of the memory device.

18. The memory device of claim 15, wherein the block lock access mode is configured to enable the memory device to prevent writing to a page of one time programmable (OTP) memory of the memory device.

19. The memory device of claim 18, wherein the one time programmable (OTP) memory comprises nonvolatile memory of the memory device

20. The memory device of claim 12, wherein the serial interface controller is configured to interpret a first byte of the serial message as the command field, a second byte of the serial message as the register address field, and a third byte of the serial message as the data field.