DYNAMIC REFERENCE CURRENT SENSING

• US 20180308553A1
• Filed: 06/29/2018
• Published: 10/25/2018
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Tien-Chun
• Granted Patent: US 10,553,288 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

A circuit includes a memory cell that generates a cell current having a cell current value, a first reference cell that generates a first current having a first current value, and a second reference cell that generates a second current having a second current value. A current generating circuit generates a reference current having a reference current value based on the first current value and the second current value, and a sense amplifier sums, at a comparison node, a third current having the cell current value and a fourth current having the reference current value. A buffer outputs a voltage on the comparison node as an output of the sense amplifier.

Claims

1. A circuit comprising:

a memory cell configured to generate a cell current having a cell current value;

a first reference cell configured to generate a first current having a first current value;

a second reference cell configured to generate a second current having a second current value;

a current generating circuit configured to generate a reference current having a reference current value based on the first current value and the second current value; and

a sense amplifier configured to sum, at a comparison node, a third current having the cell current value and a fourth current having the reference current value, wherein a buffer is configured to output a voltage on the comparison node as an output of the sense amplifier.

2. The circuit of claim 1, wherein the memory cell comprises a metal-oxide nitride-oxide semiconductor (MONOS) flash memory cell.

3. The circuit of claim 1, wherein

the first reference cell is configured to generate the first current having the first current value by storing a low logical value, and

the second reference cell is configured to generate the second current having the second current value by storing a high logical value.

4. The circuit of claim 1, wherein the current generating circuit is configured to generate the reference current having the reference current value at a midpoint between the first current value and the second current value.

5. The circuit of claim 1, wherein the current generating circuit comprises a transistor configured to generate a reference voltage by conducting an entirety of the reference current.

6. The circuit of claim 1, wherein the sense amplifier comprises:

a first transistor configured to generate the third current as a mirror of the cell current; and

a second transistor configured to generate the fourth current as a mirror of the reference current,

wherein the comparison node is between a drain of the first transistor and a drain of the second transistor.

7. The circuit of claim 1, wherein the buffer comprises a first inverter in series with a second inverter.

8. A method comprising:

receiving a first current and a second current at a reference current generating circuit;

using the reference current generating circuit, generating a reference current based on the first current and the second current;

receiving a cell current at a sense amplifier;

summing, at a comparison node of the sense amplifier, a third current having a value of the reference current and a fourth current having a value of the cell current; and

using a buffer of the sense amplifier, outputting a voltage on the comparison node as an output of the sense amplifier.

9. The method of claim 8, wherein the generating the reference current based on the first current and the second current comprises:

dividing the first current based on a first predetermined ratio;

dividing the second current based on a second predetermined ratio; and

summing the divided first current and the divided second current.

10. The method of claim 8, further comprising:

using the reference current generating circuit, generating a reference voltage from the reference current; and

using the sense amplifier, generating the third current from the reference voltage.

11. The method of claim 10, further comprising, using another sense amplifier, generating a fifth current from the reference voltage, the fifth current having the value of the reference current.

12. The method of claim 8, further comprising:

receiving another cell current at another sense amplifier; and

summing, at a comparison node of the another sense amplifier, the third current having the value of the reference current and a fifth current having a value of the another cell current.

13. The method of claim 8, wherein the outputting the voltage on the comparison node as an output of the sense amplifier comprises using the buffer to invert the voltage on the comparison node.

14. A memory array comprising:

a plurality of memory cells;

a sense amplifier comprising a buffer;

a first selection circuit configured to conduct a cell current between a selected memory cell of the plurality of memory cells and the sense amplifier;

a first reference cell configured to generate a first current having a first current value;

a second reference cell configured to generate a second current having a second current value; and

a current generating circuit configured to generate a reference current having a reference current value based on the first current value and the second current value,

wherein the sense amplifier is configured to

generate a voltage at a comparison node based on a third current having a cell current value of the cell current and a fourth current having the reference current value, and

provide the voltage at the comparison node at an output of the buffer.

15. The memory array of claim 14, wherein

the first reference cell is one first reference cell of a plurality of first reference cells,

each first reference cell of the plurality of first reference cells is configured to generate the first current having the first current value based on a first stored logical value,

the second reference cell is one second reference cell of a plurality of second reference cells, and

each second reference cell of the plurality of second reference cells is configured to generate the second current having the second current value based on a second stored logical value different from the first stored logical value.

16. The memory array of claim 15, wherein the memory array is configured to

select the first reference cell of the plurality of first reference cells corresponding to the selected memory cell of the plurality of memory cells, and

select the second reference cell of the plurality of second reference cells corresponding to the selected memory cell of the plurality of memory cells.

17. The memory array of claim 16, further comprising a decoder configured to select the memory cell of the plurality of memory cells, the first reference cell of the plurality of first reference cells, and the second reference cell of the plurality of second reference cells based on an address.

18. The memory array of claim 14, further comprising:

a second selection circuit configured to conduct the first current between the first reference cell and the current generating circuit; and

a third selection circuit configured to conduct the second current between the second reference cell and the current generating circuit.

19. The memory array of claim 14, wherein

the plurality of memory cells is one memory cell column of a plurality of memory cell columns,

the sense amplifier is one sense amplifier of a plurality of sense amplifiers, and

each sense amplifier of the plurality of sense amplifiers is configured to generate a voltage based on the reference current value and a value of a cell current of a selected memory cell of a corresponding memory cell column.

20. The memory array of claim 19, wherein

the first selection circuit is one first selection circuit of a plurality of first selection circuits, and

each first selection circuit of the plurality of first selection circuits is configured to conduct the corresponding cell current between the selected memory cell of the corresponding memory cell column and the corresponding sense amplifier of the plurality of sense amplifiers.