SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20180308982A1
• Filed: 06/25/2018
• Published: 10/25/2018
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 10,505,049 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Claims

1. (canceled)

2. A semiconductor device comprising:

an oxide semiconductor layer comprising channel formation region including a crystalline region over a substrate,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and

wherein the crystalline region has c-axis aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

3. A semiconductor device according to claim 2, further comprising a source electrode layer electrically connected to the oxide semiconductor layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

and

a first gate electrode layer below the oxide semiconductor layer with a first insulating layer therebetween.

4. A semiconductor device according to claim 2, further comprising a source electrode layer electrically connected to the oxide semiconductor layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

and

a second gate electrode layer over the oxide semiconductor layer with a second insulating layer therebetween.

5. A semiconductor device according to claim 3, further comprising a second gate electrode layer over the oxide semiconductor layer with a second insulating layer therebetween.

6. A semiconductor device according to claim 2, wherein the crystalline region has a plate-like shape.

7. A semiconductor device according to claim 2, wherein the crystalline region extends from the surface of the oxide semiconductor layer in the direction substantially perpendicular to the surface of the oxide semiconductor layer.

8. A semiconductor device comprising:

an oxide semiconductor layer comprising channel formation region including a crystalline region over a substrate,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and

wherein the crystalline region comprises a plurality of crystals with c-axis substantially parallel to each other.

9. A semiconductor device according to claim 8, further comprising a source electrode layer electrically connected to the oxide semiconductor layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

and

a first gate electrode layer below the oxide semiconductor layer with a first insulating layer therebetween.

10. A semiconductor device according to claim 8, further comprising a source electrode layer electrically connected to the oxide semiconductor layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

and

a second gate electrode layer over the oxide semiconductor layer with a second insulating layer therebetween.

11. A semiconductor device according to claim 9, further comprising a second gate electrode layer over the oxide semiconductor layer with a second insulating layer therebetween.

12. A semiconductor device according to claim 8, wherein each of the plurality of crystals has a plate-like shape.

13. A semiconductor device according to claim 8, wherein the crystalline region extends from a surface of the oxide semiconductor layer in a direction substantially perpendicular to the surface of the oxide semiconductor layer.