VERY NARROW ASPECT RATIO TRAPPING TRENCH STRUCTURE WITH SMOOTH TRENCH SIDEWALLS

• US 20180315753A1
• Filed: 05/01/2017
• Published: 11/01/2018
• Est. Priority Date: 05/01/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Karthik, Cheng, Kangguo, Hashemi, Pouya, Reznicek, Alexander
• Granted Patent: US 10,396,075 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.

Claims

1. A semiconductor structure comprising:

a plurality of epitaxial semiconductor fins located on a substrate;

a bottom spacer laterally surrounding a bottom portion of each epitaxial semiconductor fin; and

a semiconductor oxide insulator structure located between each pair of neighboring epitaxial semiconductor fins and neighboring bottom spacers and having a topmost surface located below a topmost surface of each epitaxial semiconductor fin, wherein the bottom spacer has a topmost surface that is entirely in direct contact with a bottommost surface of the semiconductor oxide insulator structure and a width that is less than a width of the semiconductor oxide insulator structure.

2. The semiconductor structure of claim 1, wherein the bottom spacer comprises a dielectric material different from that of the semiconductor oxide insulator structure.

3. The semiconductor structure of claim 1, wherein each epitaxial semiconductor fin is inverted T-shaped having a horizontal portion and a vertical portion extending upwards therefrom.

4. The semiconductor structure of claim 3, wherein the bottom spacer laterally surrounds the horizontal portion of each epitaxial semiconductor fin.

5. The semiconductor structure of claim 4, wherein the semiconductor oxide insulator structure laterally contacts sidewalls of the vertical portions of each pair of the neighboring epitaxial semiconductor fins and the neighboring bottom spacers.

6. The semiconductor structure of claim 4, each epitaxial semiconductor fin further comprises a faceted portion embedded in the substrate.

7. The semiconductor structure of claim 6, wherein the faceted portion is V-shaped.

8. The semiconductor structure of claim 1, wherein the semiconductor oxide insulator structure occupies an entire space between each pair of the neighboring epitaxial semiconductor fins and the neighboring bottom spacers.

9. The semiconductor structure claim 1, wherein the semiconductor oxide insulator structure partially fills a space between each pair of the neighboring epitaxial semiconductor fins and the neighboring bottom spacers and contacting sidewalls of each pair of the neighboring epitaxial semiconductor fins and the neighboring bottom spacers.

10. The semiconductor structure of claim 9, further comprising a semiconductor fin base portion located between each pair of the neighboring epitaxial semiconductor fins and the neighboring bottom spacers and laterally surrounded by the semiconductor oxide insulator structure, wherein the semiconductor fin base portion comprises a different semiconductor material than each epitaxial semiconductor fin.

11. The semiconductor structure of claim 10, further comprising a dielectric insulator structure atop the semiconductor fin base portion, which a topmost surface of each dielectric insulator structure is located above or below the topmost surface of each semiconductor oxide insulator structure.

12. The semiconductor structure of claim 10, further comprising a dielectric insulator structure atop each semiconductor fin base portion and each semiconductor oxide insulator structure.

13-20. -20. (canceled)